Fully preposterous gate arranger

Started by Tim Wescott in comp.arch.fpga1 day ago 19 replies

Is there synthesis software out there that'll take Verilog or other HDL and generate a netlist of 7400-series logic? To carry things one step...

Is there synthesis software out there that'll take Verilog or other HDL and generate a netlist of 7400-series logic? To carry things one step further, if you were seriously contemplating such a thing, of course you'd want the software to understand that chips and boards are of finite sizes, that propagation delays between chips and boards exist, and that board-board connections have fin...


watermarking on FPGA

Started by Hamid Kavianathar in comp.arch.fpga3 days ago 3 replies

I'm going to do a very simple watermarking. I want to embed a signature on unused LUTs. could you please tell me how I can do it? Thank you very...

I'm going to do a very simple watermarking. I want to embed a signature on unused LUTs. could you please tell me how I can do it? Thank you very much.


Freelance engineer in barcelona area

Started by Jose Miguel in comp.arch.fpga2 weeks ago

We are looking for a freelance engineer in barcelona area. Please contact to my e-Mail.

We are looking for a freelance engineer in barcelona area. Please contact to my e-Mail.


Altera MAX10 image capture application

Started by Steve Gulick in comp.arch.fpga2 weeks ago 1 reply

We are interested in finding someone to help develop an FPGA image capture application. We are using Altera's MAX10 FPGA and Arrow's BeMicro MAX10...

We are interested in finding someone to help develop an FPGA image capture application. We are using Altera's MAX10 FPGA and Arrow's BeMicro MAX10 development board. The image sensor is the MT9V034. It will transfer captured images to a Raspberry Pi over a SPI interface.


hamsterworks + lauriVosandi + X = Error

Started by Anonymous in comp.arch.fpga3 weeks ago 9 replies

Hello i am new in vhdl, but try it, I want to make pipe between OV7670 and monitor, best thing is to use code of Hamsterwork's with Lauri's...

Hello i am new in vhdl, but try it, I want to make pipe between OV7670 and monitor, best thing is to use code of Hamsterwork's with Lauri's edition http://hamsterworks.co.nz/mediawiki/index.php/Zedboard_OV7670 and http://lauri.v├Ásandi.com/hdl/zynq/zybo-ov7670-to-vga.html and want to adopt it to ML402 for Virtex-4 XC4VSX35, it requires 8 bit for each color in RGB,and bram address c


remove Xilinx webtalk

Started by Michael in comp.arch.fpga3 weeks ago 8 replies

Hi, How do I remove webtalk in Xilinx 13.1, I do run all the tools from a script not from GUI? I did run a trail license at first but now...

Hi, How do I remove webtalk in Xilinx 13.1, I do run all the tools from a script not from GUI? I did run a trail license at first but now I have a proper flexlm license! /michael


Programming waveshare core3s250e with Impact and ISE 14.1

Started by David Wade in comp.arch.fpga4 weeks ago 6 replies

Folks, Sorry if this is off-topic. I have a project that uses the above board, which has an Spartan 3E chip and an EEPROM for holding the...

Folks, Sorry if this is off-topic. I have a project that uses the above board, which has an Spartan 3E chip and an EEPROM for holding the config. If I load Impact on its own I can program the prom, press reset and the code runs. If I run the same step from within ISE it fails as I havn't assigned a file to the FPGA chip, and its on the JTAG chain and I haven't assigned a file. ...


Opinions, on this newfangled thing, please

Started by Tim Wescott in comp.arch.fpga4 weeks ago 6 replies

I just ran across...

I just ran across this: http://www.eetimes.com/author.asp? section_id=36&doc_id=1328618&_mc=sm_eet_editor_maxmaxfield&hootPostID=09e55671236236acbe4121d86c b78c72 http://tinyurl.com/zhdcerx It looks like it could be a nifty thing to use in certain circumstances, particularly where one needs a complicated analog block in little space with fairly high bandwidth (yes, I know -- it's digi


modulo 2**32-1 arith

Started by Ilya Kalistru in comp.arch.fpga1 month ago 46 replies

Hello. I need to add two unsigned numbers modulo 2**32-1. Now it's done in very inefficient way: at first clock cycle there is simple addition...

Hello. I need to add two unsigned numbers modulo 2**32-1. Now it's done in very inefficient way: at first clock cycle there is simple addition of two 32-bit unsigned numbers with 33-bit result and on second cycle if the result > = 2**32-1, we add 1 and take only 32 bits of that. Does anybody know a better way to do that?


FPGA for a beginner

Started by Hamid Kavianathar in comp.arch.fpga1 month ago 10 replies

I know this subject is very repetitive, but It's very confusing to me. I'm familiar to verilog coding and digital circuit designing but I haven't...

I know this subject is very repetitive, but It's very confusing to me. I'm familiar to verilog coding and digital circuit designing but I haven't work with FPGAs. I want to learn it. could you please help me? Thanks.


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