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IMX6 Solo - FPGA Module

Started by Mark in comp.arch.fpga5 minutes ago

Hello, I am looking for a module with Freescales iMX6 Solo and an FPGA, maybe an Artix or similar. Anyone know about such module? For now...

Hello, I am looking for a module with Freescales iMX6 Solo and an FPGA, maybe an Artix or similar. Anyone know about such module? For now no other requirements, I will look into details then. Thanks... -- Mark


Oberon Operating System + Compiler + Graphic on a Spartan 3 FPGA

Started by MGreim in comp.arch.fpga1 day ago 4 replies

Hi folks, Professor Wirth, some may know his name as the inventor of Pascal and Oberon etc., has published recently, together with Jürg...

Hi folks, Professor Wirth, some may know his name as the inventor of Pascal and Oberon etc., has published recently, together with Jürg Gutknecht and Paul Reed, an exciting project at: http://www.projectoberon.com/ Its a complete computer including a graphical operating system in a small FPGA. Its including all sources in Oberon and Verilog! The complete Oberon Code has less then 100...


Oqpsk Demod

Started by Eshwar varma in comp.arch.fpga3 days ago 1 reply

Hi all , I implement qpsk demodulator on National instruments Fpga . Now i want to Demodulate Oqpsk signal . As the difference between...

Hi all , I implement qpsk demodulator on National instruments Fpga . Now i want to Demodulate Oqpsk signal . As the difference between qpsk and oqpsk is only the delay of one bit period in q channel. Q1. Can a qpsk demodulator with some changes demodulate oqpsk data ? Q2. If it works , what changes i should make ? flow of qpsk demodulater what i made.. ...


ESP8266 based Xilinx Virtual Cable server?

Started by Wojciech M. Zabolotny in comp.arch.fpga4 days ago

Hi, I often need to access the debugged FPGA boards remotely. Now when Xilinx has made its Xilinx Virtual Cable specification...

Hi, I often need to access the debugged FPGA boards remotely. Now when Xilinx has made its Xilinx Virtual Cable specification available: http://www.xilinx.com/products/intellectual-property/xvc.html https://github.com/Xilinx/XilinxVirtualCable and when it is included in the newer versions of Vivado suite: http://forums.xilinx.com/t5/General-Technical-Discussion/XVC-Protocol-Support-In-Vi...


Clock triggered FSM

Started by electrin in comp.arch.fpga4 days ago 3 replies

Hello boys, I have got a small problem with my finite state machine which I have written in VHDL recently. I tried to create "intelligent"...

Hello boys, I have got a small problem with my finite state machine which I have written in VHDL recently. I tried to create "intelligent" counter triggered by clock with frequency 2 Hz. This counter is built in one state of FSM and is started by pushing a button on DE2 board. Firstly, whole system is in IDLE state and if I push this button, state is changed to COUNTING and counter begin t...


IIR filter bus width

Started by if.raso in comp.arch.fpga4 days ago 1 reply

Hello! I'm having trouble with 4th order butterworth filter. I'm using two cascade biquads in direct form I because it should be more reliable...

Hello! I'm having trouble with 4th order butterworth filter. I'm using two cascade biquads in direct form I because it should be more reliable on fixed point designs, as mine is. My input signal is 16-bit wide and so the output should be. My question is: how wide should the coefficients be in terms of bit? Also I'm not very confident with the bus width between adders and multipliers. Should I...


ZYNQ temperature

Started by John Larkin in comp.arch.fpga1 week ago 25 replies

Does anyone know if the ZYNQ chips have an internal high-temperature shutdown? They are behaving like they do. -- John Larkin ...

Does anyone know if the ZYNQ chips have an internal high-temperature shutdown? They are behaving like they do. -- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com


16->5 "Sort"

Started by Kevin Neilson in comp.arch.fpga2 weeks ago 23 replies

I'm trying to design a circuit (Virtex-7) which you might call either a pri= ority encoder or a sorter. This is what it should do: Given a...

I'm trying to design a circuit (Virtex-7) which you might call either a pri= ority encoder or a sorter. This is what it should do: Given a 16-bit vector with 5 bits set, create a list of 5 4-bit encoded = values of each bit set. These needn't be in order. This turns out to be a lot harder than I thought. Writing the behavioral R= TL isn't hard, but Vivado synthesizes it to 16 le


Open source Verilog BCH encoder/decoder

Started by Russell Dill in comp.arch.fpga2 weeks ago 9 replies

As part of my research, I needed a BCH encoder/decoder engine. Sadly, such = a thing has no existed under a permissive license. Even more...

As part of my research, I needed a BCH encoder/decoder engine. Sadly, such = a thing has no existed under a permissive license. Even more depressing is = that many students seem to submit Verilog or VHDL engines as a project (or = even research), but never release anything that is usable. Anyway, I'm releasing a BSD licensed Verilog BCH encoder/decoder. It offers= : * Parallel input/outp...


synthesis tool for systemc

Started by Chinix in comp.arch.fpga2 weeks ago 5 replies

hello I wish you could recommend a synthsis tool for systemC. It will be really wonderful if the tool is free for download. I know "Colexica"...

hello I wish you could recommend a synthsis tool for systemC. It will be really wonderful if the tool is free for download. I know "Colexica" and "cocentric" ,but never use them. Who can give me some tips of these tools. Thanks


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