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looking for systemC/TLM 2.0 courses

Started by alb in comp.arch.fpga5 hours ago 16 replies

Hi everyone, I apologize if this is maybe not the best audience for these kind of enquiries but I'll try anyhow. I'm looking for a good...

Hi everyone, I apologize if this is maybe not the best audience for these kind of enquiries but I'll try anyhow. I'm looking for a good SystemC/TLM 2.0 training course which is not too basic and can give me a head start for a real life project. I'm not a black belt on C++ but I'm familiar with most of its concepts on top of C (which I use quite often instead). Since we have a budget...


Parallel execution of Systemc code

Started by Anonymous in comp.arch.fpga5 hours ago 9 replies

// Testbench rst=true; wait(10, SC_MS); rst=false; in1=8; in2=2; in3=3; in4=6; sel=2; wait(50, SC_MS); cout < < "selected data:" < < out <...

// Testbench rst=true; wait(10, SC_MS); rst=false; in1=8; in2=2; in3=3; in4=6; sel=2; wait(50, SC_MS); cout < < "selected data:" < < out < < " " < < endl; rst=true; sel = 0; wait(50, SC_MS); cout < < "selected data:" < < out < < " " < < endl; I am used to VHDL which runs in parallel, but I finding it difficult to understand/if Systemc code run in parallel like the example above.


Topics for Projects on FPGA+Computer Archtecture

Started by Anonymous in comp.arch.fpga5 hours ago 4 replies

Hi, I have to work on a project related to FPGA (Altera DEI or Altera DEII) and computer architecture. Can anyone suggest good topics that I...

Hi, I have to work on a project related to FPGA (Altera DEI or Altera DEII) and computer architecture. Can anyone suggest good topics that I can work on individually (say for 3-4 months). Thank you in advance.


processor core validation

Started by alb in comp.arch.fpga5 hours ago 3 replies

Hi everyone, I was wondering if anyone can point me to some formal method to validate a soft processor core. We have the source code...

Hi everyone, I was wondering if anyone can point me to some formal method to validate a soft processor core. We have the source code (vhdl) and a simulation environment to load programs and execute them, but I'm not sure in this case code coeverage will be sufficient. What about cases like interrupt handling? I can run Dhrystone or CoreMark, but will it be sufficient? Any idea/p...


Intel in Talks to buy Altera

Started by Anonymous in comp.arch.fpga8 hours ago 6 replies

http://www.wsj.com/articles/intel-in-talks-to-buy-altera-1427485172 --------------------------------------- Posted through...

http://www.wsj.com/articles/intel-in-talks-to-buy-altera-1427485172 --------------------------------------- Posted through http://www.FPGARelated.com


Interpret a VHDL statement within a serial to paralell port

Started by nobody in comp.arch.fpga20 hours ago 2 replies

First, thank you for taking the time to consider the questions I have not a= nswered.=20 I am working on a 32 bit serial to 32 bit parallel port...

First, thank you for taking the time to consider the questions I have not a= nswered.=20 I am working on a 32 bit serial to 32 bit parallel port which reads from an= ADC. Currently looking to find a better solution, and I searched for prede= fined vhdl module with little success. I stumbled upon Macros, SR16CE, whic= h utilize primitives but they seem to be schematic oriented and not availab...


Parametrized, synthesizable FFT engine

Started by Anonymous in comp.arch.fpga4 days ago 1 reply

Hi, I have just published a simple, parametrized synthesizable FFT engine, which allows the user to define the length of FFT (as power of...

Hi, I have just published a simple, parametrized synthesizable FFT engine, which allows the user to define the length of FFT (as power of two), define the format of the numbers and adjust the engine to the latency of the "butterfly block". I couldn't find similar open source solution, so I decided to publish mine. Of course it is the user's responsibility to implement the "butterfly block"...


DDS

Started by maxascent in comp.arch.fpga1 week ago 10 replies

What is the best way to implement a multi channel DDS. I need a DDS that has 8 channels that are time-multiplexed. I am using a Sparatn 6....

What is the best way to implement a multi channel DDS. I need a DDS that has 8 channels that are time-multiplexed. I am using a Sparatn 6. Thanks --------------------------------------- Posted through http://www.FPGARelated.com


Multicycle paths using clock enable (in Synplify Pro)

Started by Anonymous in comp.arch.fpga2 weeks ago 2 replies

Hi all, I am looking for a generic set of TCL commands (for Synplify) to constrain = _all_ flip-flops which are connected to the same clock...

Hi all, I am looking for a generic set of TCL commands (for Synplify) to constrain = _all_ flip-flops which are connected to the same clock enable net with the = same timing constraints. This would be much easier than constraining every = single net on its own. I suppose there should be a set of TCL commands to d= efine those timing constraints. Let me give you an example: I have a CLK fre...


Handel-C to VHDL

Started by Ahmed Ablak in comp.arch.fpga2 weeks ago 2 replies

When I generate VHDL from Handel-C. I always end up with an empty VHDL file, did any one face this problem? and how to solve it? Thanks

When I generate VHDL from Handel-C. I always end up with an empty VHDL file, did any one face this problem? and how to solve it? Thanks


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