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Handel-C to VHDL

Started by Ahmed Ablak in comp.arch.fpga5 days ago 6 replies

When I generate VHDL from Handel-C. I always end up with an empty VHDL file, did any one face this problem? and how to solve it? Thanks

When I generate VHDL from Handel-C. I always end up with an empty VHDL file, did any one face this problem? and how to solve it? Thanks


Finally! A Completely Open Complete FPGA Toolchain

Started by rickman in comp.arch.fpga2 weeks ago 58 replies

I am very impressed. I was reading about Antti's incredibly tiny FPGA project board and saw a mention of a FOSS FPGA toolchain. Not just the...

I am very impressed. I was reading about Antti's incredibly tiny FPGA project board and saw a mention of a FOSS FPGA toolchain. Not just the compiler, but the entire bitstream generation! http://hackaday.com/2015/07/03/hackaday-prize-entry-they-make-fpgas-that-small/ Several people have built on each other's work to provide "a fully open source Verilog to bitstream development tool c...


fifo or sdram bug?

Started by kaz in comp.arch.fpga2 weeks ago 29 replies

In our system a signal is passed through a couple of fifos inside FPGA and then onto external sdram to be read by application software. All looks...

In our system a signal is passed through a couple of fifos inside FPGA and then onto external sdram to be read by application software. All looks ok except that some units in the field show occasional errors in that signal read from sdram. The error is as follows: odd samples are offset by 8 samples from the even. So if we remove this offset then signal looks ok. I can't reproduce the error in ...


Strange way to route design.

Started by Ilya Kalistru in comp.arch.fpga2 weeks ago 4 replies

Hello, colleagues. I'm fixing issues of the design with many clocks and its interaction on Art= ix7 FPGA. In order to move data from one clock...

Hello, colleagues. I'm fixing issues of the design with many clocks and its interaction on Art= ix7 FPGA. In order to move data from one clock domain to another I'm using = double-port distributed memory with synchronous read, but this design doesn= 't meet timing constrains (250Mhz). Critical path consists of a trigger of = the read address of the Distributed RAM, a Distributed Ram primitive...


Is it possible to have a parameterized verilog module name in verilog or systemverilog?

Started by Anonymous in comp.arch.fpga3 weeks ago 6 replies

Hi, I am trying create verilog module that can support parameterized instance name. I understand that the signal width and other such things...

Hi, I am trying create verilog module that can support parameterized instance name. I understand that the signal width and other such things can be parameterized. But can we also parameterize the module instance name? In following code, I am curious if there is any way SomeDynamicInstanceName can be parameterized also? I can try to use system verilog if that can help here M


Picking the best synthesis result before implementation

Started by James07 in comp.arch.fpga4 weeks ago 10 replies

Out of curiosity, I wrote a script to explore with different options in the Vivado software (2014.4), especially on the synthesis options under...

Out of curiosity, I wrote a script to explore with different options in the Vivado software (2014.4), especially on the synthesis options under SYNTH_DESIGN, like FSM_extraction, MAX_BRAM etc. The script stops after synthesis, just enough to get the timing estimate. I explore everything except the directive because it seems like you use the directive, you cannot manually set the opt


Image Compression in an FPGA

Started by rickman in comp.arch.fpga4 weeks ago 8 replies

Someone is looking to generate compressed images in an FPGA to display graph data on a browser. Looking around the GIF, TIFF or PNG formats...

Someone is looking to generate compressed images in an FPGA to display graph data on a browser. Looking around the GIF, TIFF or PNG formats seem rather straightforward to implement. Anyone know of an implementation of one of these in an HDL? It doesn't need to implement the entire standard, just enough to generate one image style. -- Rick


FPGA board to interface with ADC (>10 GHz) and generate 5Gbps PRBS

Started by vmenon in comp.arch.fpga1 month ago

Hello all, I am designing a circuit that requires a 10 GHz ADC and a FPGA to generate a 5 Gbps PRBS. I am not able to find a high speed ADC and...

Hello all, I am designing a circuit that requires a 10 GHz ADC and a FPGA to generate a 5 Gbps PRBS. I am not able to find a high speed ADC and a supporting FPGA evaluation board. Does anyone know/ can recommend a board? Thanks in advance, V


Free Lattice FPGA

Started by Michael Kellett in comp.arch.fpga1 month ago

I'm turning out a cupboard and have found 10 off Lattice LFECP10E-4FN256C - still sealed in dry packs. Location SW Scotland - seems a shame to...

I'm turning out a cupboard and have found 10 off Lattice LFECP10E-4FN256C - still sealed in dry packs. Location SW Scotland - seems a shame to bin them - I'll try to give them away at the Wuthering Bytes jolly in Hebden Bridge at the end of Septemebr unless someone here would like them first. Contact me direct if you are interested. mk AT mkesc DOT co DOT uk Michael Kellett


Aligning symbols with IDELAY / ISERDES in Xilinx 7-series devices.

Started by Mike Field in comp.arch.fpga2 months ago 1 reply

Hi, I'm working in Artix-7 and I've got a workable way to adjust the bitslip and IDELAY tap settings to lock onto an incoming TMDS encoded...

Hi, I'm working in Artix-7 and I've got a workable way to adjust the bitslip and IDELAY tap settings to lock onto an incoming TMDS encoded stream, but is there a better way? Currently I count the symbol error rate on the link, and if the rate of bad symbols is greater than 1:2^20 I then move on to a higher delay tap setting. If the delay's tap setting wraps I also assert bi


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