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What's the name of this circuit?

Started by Guy Eschemann in comp.arch.fpga1 hour ago 1 reply

Hi, I need to design a sub-module with 128-bit input and output stream interfaces (4 DWORDs/cycle) which can split the stream at arbitrary DWORD...

Hi, I need to design a sub-module with 128-bit input and output stream interfaces (4 DWORDs/cycle) which can split the stream at arbitrary DWORD boundaries. Example input: DW3 DW2 DW1 DW0 DW7 DW6 DW5 DW4 DWB DWA DW9 DW8 Example output (stream was split after DW4 and re-starts with a full 128-bit word): DW3 DW2 DW1 DW0 - - - DW4 DW8 DW7 DW6 DW5 - DWB DWA DW9 ...


Installation of Vivado on Debian Linux on x86_64 machine

Started by Anonymous in comp.arch.fpga1 day ago

Hi, When I try to install Xilinx Vivado on 64-bit x86_64 machine, I get the following error: $ ./xsetup ERROR: This installation is not...

Hi, When I try to install Xilinx Vivado on 64-bit x86_64 machine, I get the following error: $ ./xsetup ERROR: This installation is not supported on 32 bit platforms. The reason is, that xsetup erroneously uses "uname -i" instead of "uname -m" to check the architecture: # ERROR out if this installation is running on 32 bit OS # and does not support 32 bit installation if [ "$(uname...


SVF test vector injection - generating SVF files

Started by Johann Klammer in comp.arch.fpga6 days ago 3 replies

Good morning, I was trying to run some test vectors on an ATF1504ASVL_A44 CPLD. Even found some BSDL files on the net(no Idea if they're...

Good morning, I was trying to run some test vectors on an ATF1504ASVL_A44 CPLD. Even found some BSDL files on the net(no Idea if they're correct, tho'). I have vectors like this: V0001 NLLNLLNLNLL1NNNNNNNHNNNNNNNNNNNNNN0NNNNNNLLL* V0002 NLLNLLNLNLL0NNNNNNNHNNNNNNNNNNNNNN0NNNNNNLLL* V0003 NLLNLLNLNLL0NNNNNNNLNNNNNNNNNNNNNN1NNNNNNHLL* [...] They are generated from a verilog sim. Fro...


does anybody use systemc in FPGA flow?

Started by pini_kr in comp.arch.fpga1 week ago 4 replies

Hi I just wanted to know if people use systemc in FPGA flow. systemc can be used for cycle accurate simulation, where it can replace RTL. In...

Hi I just wanted to know if people use systemc in FPGA flow. systemc can be used for cycle accurate simulation, where it can replace RTL. In this mode test-benches will usually take advantage of c++ and SCV (for writing constraints). For big designs where RTL completion takes a lot of time systemc can be used for LT or AT simulations ( Loosely Timed, Approximately Timed TLM). Pini -------...


Speed of GTX transceivers in Kintex 7 in FBG package?

Started by Anonymous in comp.arch.fpga1 week ago

Hi, I have seen contradictory data about speed of GTX transceivers in Kintex 7 in FBG packages: 1. The datasheet (...

Hi, I have seen contradictory data about speed of GTX transceivers in Kintex 7 in FBG packages: 1. The datasheet ( http://www.xilinx.com/support/documentation/data_sheets/ds182_Kintex_7_Data_Sheet.pdf , page 54 ) states that the maximum speed is 6.6 Gb/s 2. The answer record http://www.xilinx.com/support/answers/50299.html states explicitly: " Limit the maximum line rate to 6.6 Gb


Conditional Interpretation of VHDL

Started by David Wade in comp.arch.fpga1 week ago 14 replies

I have a small project that produces a clone of the "BABY" computer at MOSI. I want to be able to produce two versions of the code, one which...

I have a small project that produces a clone of the "BABY" computer at MOSI. I want to be able to produce two versions of the code, one which displays on a VGA screen and another which uses a Luminescent display. To do this I need to be able to set different output signals depending on the way its built. At present I am building two different projects and keeping them both up to date...


Free Webinar: Overcome the challenges of powering FPGAs

Started by Anonymous in comp.arch.fpga2 weeks ago

Join UBM and Tech Online next week for a free webinar: =20 Overcome the challenges of powering FPGAs. =20 June 25th 11:00am PST/2:00pm...

Join UBM and Tech Online next week for a free webinar: =20 Overcome the challenges of powering FPGAs. =20 June 25th 11:00am PST/2:00pm EST An FPGA typically needs three or more voltage rails, each with a different = current requirement that depends upon the functionality being implemented i= n the design. This webinar will review the specifications that are needed t= o power FPGAs as wel...


Deadline Approaching: The Global Technology Management Conference (GTMC2015) - USA

Started by Anonymous in comp.arch.fpga3 weeks ago

The Global Technology Management Conference (GTMC2015) Bemidji State University, Minnesota, USA July 15 - 17,...

The Global Technology Management Conference (GTMC2015) Bemidji State University, Minnesota, USA July 15 - 17, 2015 http://t.co/Wq3W22S8V8 You are invited to participate in The Global Technology Management Conference (GTMC2015) that will be held at Bemidji State University, Minnesota, USA on July 15 - 17, 2015. The event will be held over three days, with presentations delivered by r


Is it possible to have a parameterized verilog module name in verilog or systemverilog?

Started by Anonymous in comp.arch.fpga3 weeks ago 5 replies

Hi, I am trying create verilog module that can support parameterized instance name. I understand that the signal width and other such things...

Hi, I am trying create verilog module that can support parameterized instance name. I understand that the signal width and other such things can be parameterized. But can we also parameterize the module instance name? In following code, I am curious if there is any way SomeDynamicInstanceName can be parameterized also? I can try to use system verilog if that can help here M


Energy efficiency of FPGA vs GPU vs CPU

Started by computerarchitect in comp.arch.fpga3 weeks ago 1 reply

This survey paper published in ACM Computing Surveys 2015 compares GPU with FPGA and CPU on energy efficiency metric. Most papers reviewed in the...

This survey paper published in ACM Computing Surveys 2015 compares GPU with FPGA and CPU on energy efficiency metric. Most papers reviewed in the survey report that FPGA is more energy efficient than GPU, which, in turn, is more energy efficient than CPU. https://www.academia.edu/6644474/A_Survey_of_Methods_For_Analyzing_and_Improving_GPU_Energy_Efficiency


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