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Does each core of 8-core Intel processor has an independent floating X87 unit?

Started by Weng Tianxiang in comp.arch.fpga3 days ago 1 reply

Hi, Does each core of 8-core Intel processor has an independent floating X87 unit? Here are some texts from Intel latest...

Hi, Does each core of 8-core Intel processor has an independent floating X87 unit? Here are some texts from Intel latest datasheet: Intel(R) Core(tm) i7 Processor Family for LGA2011-v3 Socket Datasheet - Volume 1 of 2 Processor Feature Details *Up to 8 execution cores *Each core supports two threads (Intel(R) Hyper-Threading Technology) *32 KB instruction and 32 KB data first-level...


Directly connect two XAUI ports inside FPGA

Started by Guenther Wenninger in comp.arch.fpga3 days ago 1 reply

Hi all, to implement something like a passthru mode, we want to directly connect two XAUI ports inside the FPGA. The FPGA is a Xilinx...

Hi all, to implement something like a passthru mode, we want to directly connect two XAUI ports inside the FPGA. The FPGA is a Xilinx Virtex-6. Therefor we did instantiate two XAUI-cores and connected txd/txc from one core with the rxd/rxc from the other core and vice versa. Because both cores use a different refclk we simply added two synchronizer FFs in between. In our test-design t...


Xilinx Aurora link splitter

Started by Hendrik van der Heijden in comp.arch.fpga3 days ago 2 replies

Hi, I'm a software guy and now that I have a hardware problem, I hope to find some good advice here. There are two devices A and B...

Hi, I'm a software guy and now that I have a hardware problem, I hope to find some good advice here. There are two devices A and B connected using Aurora link (single lane, full duplex) over SFP + optical LC cables. Data transfer is mostly A-> B. Now I want to tap into this link transparently, so that device C gets a copy of (at least) everything that A sends. C is fast enough to rece


Choosing the right FPGA board

Started by FrewCen in comp.arch.fpga5 days ago 9 replies

Hello! I have several years of experience in programming, and I'd like to move on to FPGAs to enjoy more fun. As I have a limited budget...

Hello! I have several years of experience in programming, and I'd like to move on to FPGAs to enjoy more fun. As I have a limited budget for my playing with electronics, I'd like to choose the most versatile board for the best price with a decent support from manufacturer. I'm a student, so I guess the academic prices apply for me. I tried to do my own research on google. What I w...


FPGA / DSP - Urgent need in Orange County, CA

Started by chipcareers.com in comp.arch.fpga5 days ago 1 reply

This is an urgent opening with a well funded start-up in Orange County, CA. They are backed by the top Telecom VC. Basically looking for a DSP...

This is an urgent opening with a well funded start-up in Orange County, CA. They are backed by the top Telecom VC. Basically looking for a DSP Engineer and FPGA/DSP Design Engineer. Some of the leading people from Broadcom, Globespan/Conexant, and others are working on a very interesting next generation product. High salary and options for the right person. If you know of anyone that may...


Division by a constant

Started by Rob Gaddi in comp.arch.fpga1 week ago 10 replies

So I just had a thought. Most synthesis tools (in VHDL, and I assume in Verilog) will allow you to use the division operator to perform...

So I just had a thought. Most synthesis tools (in VHDL, and I assume in Verilog) will allow you to use the division operator to perform truncating division by a constant in synthesizable code, so long as that constant is a power of 2. That seems like a reasonable restriction; that you can only divide when it's just a right shift, right up until you think a bit longer. Because I do s...


does anybody use systemc in FPGA flow?

Started by pini_kr in comp.arch.fpga2 weeks ago 3 replies

Hi I just wanted to know if people use systemc in FPGA flow. systemc can be used for cycle accurate simulation, where it can replace RTL. In...

Hi I just wanted to know if people use systemc in FPGA flow. systemc can be used for cycle accurate simulation, where it can replace RTL. In this mode test-benches will usually take advantage of c++ and SCV (for writing constraints). For big designs where RTL completion takes a lot of time systemc can be used for LT or AT simulations ( Loosely Timed, Approximately Timed TLM). Pini -------...


Aurora IP 8B10B problem with TVALID

Started by ponnagantiraju in comp.arch.fpga2 weeks ago

I am getting unexpected SOF(AXI_OP_TVALID) signal down as shown in the figure (find the fig in attachments). I have taken example design as...

I am getting unexpected SOF(AXI_OP_TVALID) signal down as shown in the figure (find the fig in attachments). I have taken example design as a reference. In the dsign, I fixed frame size (X"07"). But in Rx, SOF is getting down near EOF( as in fig).I want to receive complete frame data beat.In the waveform,SOF means VALID, EOF means TLAST.I am trying to get complete data from SOF to EOF as TX side...


Call for Participation: ACM/IEEE Symposium on Architectures for Networking and Communications Systems

Started by Eric Keller in comp.arch.fpga2 weeks ago

> > > CALL FOR PARTICIPATION -- ANCS 2015 < < < The 11th ACM/IEEE Symposium on Architectures for Networking and Communications...

> > > CALL FOR PARTICIPATION -- ANCS 2015 < < < The 11th ACM/IEEE Symposium on Architectures for Networking and Communications Systems http://www.ancsconf.org May 7-8, 2015 at Oakland, CA, USA. Co-Located with the 12th USENIX Symposium on Networked Systems Design and Implementation (NSDI) https://www.usenix.org/conference/nsdi15 Venue: Oakland Marriott City Center 1001 Broadway Oak


Microblaze with AXI streaming interfaces

Started by pad007 in comp.arch.fpga3 weeks ago

Hello, I am trying to connect my IP to the microblaze by AXI streaming protocol. I have connected my IP to the microblaze using the...

Hello, I am trying to connect my IP to the microblaze by AXI streaming protocol. I have connected my IP to the microblaze using the AXI streaming link M0_AXIS in XPS. But it seems that the microblaze does not accept any data ie., the s_axis_tready never goes high. The below is the code for micro blaze. while(1){ print("waiting for a packet...n"); getfslx(temp,0,FSL_NONB...


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