Comp.Arch.FPGA

Xilinx Artix-7 availability
by Arne Pagel sent on 04:2- -0-12-20
did anybody hear something about the availability about the Xilinx Artix-7 series? Especially I a... 

Design Notation VHDL or Verilog?
by vsh sent on 03:2- -0-12-20
any comments on either VHDL or Verilog? ... 

Difference between Xilinx isim and modelsim
by guenter sent on 02:2- -0-12-20
Is it allowed to pass a member of a std_logic_vector to the rising_edge function? When doing this, ...