>  ... If you 
> wanted to push the clock frequency, and especially if you were going to 
> run multiple boards, then arranging things for best propagation delay 
> would get -- interesting.
> 

This reminds me of the odd shape of the Cray 1.  Effective, but probably a pain to assemble and debug.  I think the bus wires of the Cray were also cut to the same length to reduce skew.

On Fri, 05 Feb 2016 13:19:29 +0000, Theo Markettos wrote:

> BobH <wanderingmetalhead.nospam.please@yahoo.com> wrote:
>> On 02/03/2016 09:01 PM, Tim Wescott wrote:
>> > Only in the absence of significant delays due to board layout.  If
>> > you wanted to push the clock frequency, and especially if you were
>> > going to run multiple boards, then arranging things for best
>> > propagation delay would get -- interesting.
>> 
>> In any event, parameter extraction for timing analysis would be a real
>> trick! It should at least be possible on a PCB, wire wrap would
>> probably just be a default guess.
> 
> It's possible - tools like HyperLynx do it.  For multiple boards you can
> throw in the R-L-C of the interconnect as additional passive components
> in the model.  If you're really fussy, Ansys will give you 3D E-M
> simulation to extract them from your 3D geometry.
> 
> What this workflow isn't is closed loop.  While you can construct a
> toolchain:
> 
> HDL -> synthesis -> technology mapping -> schematic -> board layout ->
> parameter extraction
> 
> the design is roughly waterfall except perhaps the board layout stage,
> which is informed by timing extraction.  In other words there is no
> mechanism to make changes to the logic mapping based on timing of
> placement: in the PCB tool you can pin or package swap but that's about
> it.
> 
> FPGA tools are better at going back up and redoing the synthesis if the
> place and route doesn't meet timing.  PCB tools generally don't.

Well, that gives us some more guidance for making our FPGA fully 
preposterous!  To be fully preposterous, a gate arranger must be moving 
the 7400-series parts around on multiple boards and taking backplane 
delays into account.

-- 

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

BobH <wanderingmetalhead.nospam.please@yahoo.com> wrote:
> On 02/03/2016 09:01 PM, Tim Wescott wrote:
> > Only in the absence of significant delays due to board layout.  If you
> > wanted to push the clock frequency, and especially if you were going to
> > run multiple boards, then arranging things for best propagation delay
> > would get -- interesting.
> 
> In any event, parameter extraction for timing analysis would be a real 
> trick! It should at least be possible on a PCB, wire wrap would probably 
> just be a default guess.

It's possible - tools like HyperLynx do it.  For multiple boards you can
throw in the R-L-C of the interconnect as additional passive components in
the model.  If you're really fussy, Ansys will give you 3D E-M simulation to
extract them from your 3D geometry.

What this workflow isn't is closed loop.  While you can construct a
toolchain: 

HDL -> synthesis -> technology mapping -> schematic -> board layout ->
parameter extraction

the design is roughly waterfall except perhaps the board layout stage, which
is informed by timing extraction.  In other words there is no mechanism to
make changes to the logic mapping based on timing of placement: in the PCB
tool you can pin or package swap but that's about it.

FPGA tools are better at going back up and redoing the synthesis if
the place and route doesn't meet timing.  PCB tools generally don't.

Theo

On 02/03/2016 09:01 PM, Tim Wescott wrote:
> Only in the absence of significant delays due to board layout.  If you
> wanted to push the clock frequency, and especially if you were going to
> run multiple boards, then arranging things for best propagation delay
> would get -- interesting.

In any event, parameter extraction for timing analysis would be a real 
trick! It should at least be possible on a PCB, wire wrap would probably 
just be a default guess.

BobH

On Wed, 03 Feb 2016 18:32:37 -0800, jonesandy wrote:

> Don't confuse synthesis with placement and routing.
> 
> Some board-level schematic capture systems (like Cadence Concept/Alegro
> DE) compile a schematic into a list of "sections" (logical
> subcomponents) and then "package" these subcomponents into devices (e.g.
> four 2-input NAND gates into one 7400 device) for layout, which can then
> re-assign subcomponents to "swap gates" between packages during PWB
> layout. The "packager" understands constraints like common logical pins
> between multiple sections (like the common clock and OE pins on a '374
> octal register) so that two gates (registers in the case of a '374) can
> only be packaged into the same device if they share the same clock and
> OE signals.
> 
> With such a back-end packaging system, the synthesis tool would only
> need to map to single gates/functions, which would probably give better
> results, and could be "packaged" by a conventional schematic capture &
> layout system.

Only in the absence of significant delays due to board layout.  If you 
wanted to push the clock frequency, and especially if you were going to 
run multiple boards, then arranging things for best propagation delay 
would get -- interesting.

-- 
www.wescottdesign.com

Don't confuse synthesis with placement and routing.=20

Some board-level schematic capture systems (like Cadence Concept/Alegro DE)=
 compile a schematic into a list of "sections" (logical subcomponents) and =
then "package" these subcomponents into devices (e.g. four 2-input NAND gat=
es into one 7400 device) for layout, which can then re-assign subcomponents=
 to "swap gates" between packages during PWB layout. The "packager" underst=
ands constraints like common logical pins between multiple sections (like t=
he common clock and OE pins on a '374 octal register) so that two gates (re=
gisters in the case of a '374) can only be packaged into the same device if=
 they share the same clock and OE signals.=20

With such a back-end packaging system, the synthesis tool would only need t=
o map to single gates/functions, which would probably give better results, =
and could be "packaged" by a conventional schematic capture & layout system=
.

Andy

On Mon, 25 Jan 2016 16:55:52 +0000, Aleksandar Kuktin wrote:

> On Mon, 25 Jan 2016 09:37:51 -0500, Walter Banks wrote:
> 
>> On 19/01/2016 7:24 PM, BobH wrote:
>>> On 01/18/2016 07:37 PM, Tim Wescott wrote:
>>>> Is there synthesis software out there that'll take Verilog or other
>>>> HDL and generate a netlist of 7400-series logic?
>>>
>>> Interesting idea, but moving in the opposite direction of progress
>>> (grin). You could probably make a technology library for a standard
>>> synthesis package, but handling the multiple gates/package might be a
>>>  problem.
>>>
>>>
>>>> So -- has it been done, perhaps by someone with way too much time on
>>>> their hands?  How big is an ARM M1 core when it's implemented in
>>>> discrete logic chips that are currently available in the DigiKey
>>>> catalog?  And how fast?
>>>>
>>> It would probably be about the size of a PDP11-34 and run at 10MHz
>>> instead of 50MHz, but this is very much a WAG.
>> 
>> Back in the day when I was actually building computers out of such
>> logic 10MHz was a significant challenge.
>> 
>> Just thinking about makes me cringe. When I finally created a 10Mps
>> special purpose ISA it was a real achievement. Tim clearly you have far
>> too much time on your hands just thinking about such stuff:) Other than
>> ... "With miniaturization we put all this stuff in there in the last 40
>> years." Why?
>> 
>> w..
> 
> I've actually thought about this as well. I also thought about how good
> it would be to also build core memory and therefore construct a full
> Iron Age computer.
> 
> I would do this to create a known device with no non-inspectable
> components, which here means "no backdoors". Then I would use it to
> compile more integrated systems culminating with a fast FPGA-based
> device and/or a known safe compiler lineage.
> 
> However, the project is not a priority. :)

I suspect that even those "iron age" computers had back doors.

-- 
www.wescottdesign.com

On Mon, 25 Jan 2016 09:37:51 -0500, Walter Banks wrote:

> On 19/01/2016 7:24 PM, BobH wrote:
>> On 01/18/2016 07:37 PM, Tim Wescott wrote:
>>> Is there synthesis software out there that'll take Verilog or other
>>> HDL and generate a netlist of 7400-series logic?
>>
>> Interesting idea, but moving in the opposite direction of progress
>> (grin). You could probably make a technology library for a standard
>> synthesis package, but handling the multiple gates/package might be a
>>  problem.
>>
>>
>>> So -- has it been done, perhaps by someone with way too much time on
>>> their hands?  How big is an ARM M1 core when it's implemented in
>>> discrete logic chips that are currently available in the DigiKey
>>> catalog?  And how fast?
>>>
>> It would probably be about the size of a PDP11-34 and run at 10MHz
>> instead of 50MHz, but this is very much a WAG.
> 
> Back in the day when I was actually building computers out of such logic
> 10MHz was a significant challenge.
> 
> Just thinking about makes me cringe. When I finally created a 10Mps
> special purpose ISA it was a real achievement. Tim clearly you have far
> too much time on your hands just thinking about such stuff:) Other than
> ... "With miniaturization we put all this stuff in there in the last 40
> years." Why?
> 
> w..

I've actually thought about this as well. I also thought about how good 
it would be to also build core memory and therefore construct a full Iron 
Age computer.

I would do this to create a known device with no non-inspectable 
components, which here means "no backdoors". Then I would use it to 
compile more integrated systems culminating with a fast FPGA-based device 
and/or a known safe compiler lineage.

However, the project is not a priority. :)

On Mon, 25 Jan 2016 09:37:51 -0500, Walter Banks wrote:

> On 19/01/2016 7:24 PM, BobH wrote:
>> On 01/18/2016 07:37 PM, Tim Wescott wrote:
>>> Is there synthesis software out there that'll take Verilog or other
>>> HDL and generate a netlist of 7400-series logic?
>>
>> Interesting idea, but moving in the opposite direction of progress
>> (grin). You could probably make a technology library for a standard
>> synthesis package, but handling the multiple gates/package might be a
>>  problem.
>>
>>
>>> So -- has it been done, perhaps by someone with way too much time on
>>> their hands?  How big is an ARM M1 core when it's implemented in
>>> discrete logic chips that are currently available in the DigiKey
>>> catalog?  And how fast?
>>>
>> It would probably be about the size of a PDP11-34 and run at 10MHz
>> instead of 50MHz, but this is very much a WAG.
> 
> Back in the day when I was actually building computers out of such logic
> 10MHz was a significant challenge.
> 
> Just thinking about makes me cringe. When I finally created a 10Mps
> special purpose ISA it was a real achievement. Tim clearly you have far
> too much time on your hands just thinking about such stuff:) Other than
> ... "With miniaturization we put all this stuff in there in the last 40
> years." Why?

Why?  Why build vacuum-tube electronics?  Why build hot rods out of cars 
from the 1930s?

Why not?

(Note that _I_ do not wish to be the one doing this...)

-- 
www.wescottdesign.com

On 19/01/2016 7:24 PM, BobH wrote:
> On 01/18/2016 07:37 PM, Tim Wescott wrote:
>> Is there synthesis software out there that'll take Verilog or other
>> HDL and generate a netlist of 7400-series logic?
>
> Interesting idea, but moving in the opposite direction of progress
> (grin). You could probably make a technology library for a standard
> synthesis package, but handling the multiple gates/package might be a
>  problem.
>
>>
>> So -- has it been done, perhaps by someone with way too much time
>> on their hands?  How big is an ARM M1 core when it's implemented in
>> discrete logic chips that are currently available in the DigiKey
>> catalog?  And how fast?
>>
> It would probably be about the size of a PDP11-34 and run at 10MHz
> instead of 50MHz, but this is very much a WAG.

Back in the day when I was actually building computers out of such logic
10MHz was a significant challenge.

Just thinking about makes me cringe. When I finally created a 10Mps
special purpose ISA it was a real achievement. Tim clearly you have far
too much time on your hands just thinking about such stuff:) Other than
... "With miniaturization we put all this stuff in there in the last 40
years." Why?

w..