Multicycle paths using clock enable (in Synplify Pro)

Hi all,

I am looking for a generic set of TCL commands (for Synplify) to constrain =
_all_ flip-flops which are connected to the same clock enable net with the =
same timing constraints. This would be much easier than constraining every =
single net on its own. I suppose there should be a set of TCL commands to d=
efine those timing constraints.
Let me give you an example: I have a CLK frequency of 40 MHz (rising edge) =
and all flip-flops in this example design are connected to a clock enable s=
ignal. This enable signal takes care that only every second rising edge clo=
ck signal is considered. Therefore I want to define a multi-cycle path cons=
traint of "2" for all those flip-flops connected to this clock enable signa=
l.

Does anybody have suggestions for such a set of TCL-based timing constraint=
s?

Thanks in advance.

I don't know about Synplify but this is an altera timequest example
(timequest resource 
center)

set_multicycle_path 2 -to [get_fanouts [get_pins enable_reg|q*] 
-through [get_pins -hierarchical *|*ena*]] -end -setup

set_multicycle_path 1 -to [get_fanouts [get_pins enable_reg|q*] 
-through [get_pins -hierarchical *|*ena*]] -end –hold


Kaz	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Am Freitag, 13. M=E4rz 2015 14:46:51 UTC+1 schrieb kaz:
> I don't know about Synplify but this is an altera timequest example
> (timequest resource=20
> center)
>=20
> set_multicycle_path 2 -to [get_fanouts [get_pins enable_reg|q*]=20
> -through [get_pins -hierarchical *|*ena*]] -end -setup
>=20
> set_multicycle_path 1 -to [get_fanouts [get_pins enable_reg|q*]=20
> -through [get_pins -hierarchical *|*ena*]] -end -hold
>=20
>=20
> Kaz	  =20
> 				=09
> ---------------------------------------	=09
> Posted through http://www.FPGARelated.com

Hello Kaz,
thank you for your example. Unfortunately the command "get_fanouts" is not =
available within Synplify. In the meantime I have developed a semi-automati=
c approach by using the TCL command "expand". I am generating a list of seq=
uential modules which are enabled by specific clock enable signal:
expand -hier -from {n:*CE*} -seq
With the help of a few editor macros I am building the timing contraints fi=
le. And it works!