Interpret a VHDL statement within a serial to paralell port

First, thank you for taking the time to consider the questions I have not a=
nswered.=20
I am working on a 32 bit serial to 32 bit parallel port which reads from an=
 ADC. Currently looking to find a better solution, and I searched for prede=
fined vhdl module with little success. I stumbled upon Macros, SR16CE, whic=
h utilize primitives but they seem to be schematic oriented and not availab=
le inside the ISE 8.2i, windows xp os.=20

Question: Do common VHDL constructs exist in some library within the Xilinx=
 folder file structure?

Stumbling onto some help files within Xilinx website,http://www.csit-sun.pu=
b.ro/courses/Masterat/Xilinx%20Synthesis%20Technology/toolbox.xilinx.com/do=
csan/xilinx4/data/docs/xst/hdlcode8.html, I found what I think I was lookin=
g for, however I need some help interpreting the VHDL statement that does e=
verything, [line 13]:

8-bit Shift-Left Register with Positive-Edge Clock, Serial In, and Parallel=
 Out
Note For this example XST will infer SRL16.

1.library ieee;=20
2.use ieee.std_logic_1164.all;=20
=20
3.entity shift is =20
4. port(C, SI : in  std_logic;=20
5.        PO : out std_logic_vector(7 downto 0));=20
6.end shift;=20
7.architecture archi of shift is=20
8.  signal tmp: std_logic_vector(7 downto 0);=20
9.  begin=20
10.    process (C)=20
11.      begin =20
12.        if (C'event and C=3D'1') then =20
13.         tmp <=3D tmp(6 downto 0)& SI;=20
14.        end if;=20
15.    end process;=20
16.    PO <=3D tmp;=20
17.end archi;=20

Question:How does line 13 seem to do so much?

On Friday, March 27, 2015 at 5:14:44 PM UTC-5, nobody wrote:
> First, thank you for taking the time to consider the questions I have not=
 answered.=20
> I am working on a 32 bit serial to 32 bit parallel port which reads from =
an ADC. Currently looking to find a better solution, and I searched for pre=
defined vhdl module with little success. I stumbled upon Macros, SR16CE, wh=
ich utilize primitives but they seem to be schematic oriented and not avail=
able inside the ISE 8.2i, windows xp os.=20
>=20
> Question: Do common VHDL constructs exist in some library within the Xili=
nx folder file structure?
>=20
> Stumbling onto some help files within Xilinx website,http://www.csit-sun.=
pub.ro/courses/Masterat/Xilinx%20Synthesis%20Technology/toolbox.xilinx.com/=
docsan/xilinx4/data/docs/xst/hdlcode8.html, I found what I think I was look=
ing for, however I need some help interpreting the VHDL statement that does=
 everything, [line 13]:
>=20
> 8-bit Shift-Left Register with Positive-Edge Clock, Serial In, and Parall=
el Out
> Note For this example XST will infer SRL16.
>=20
> 1.library ieee;=20
> 2.use ieee.std_logic_1164.all;=20
> =20
> 3.entity shift is =20
> 4. port(C, SI : in  std_logic;=20
> 5.        PO : out std_logic_vector(7 downto 0));=20
> 6.end shift;=20
> 7.architecture archi of shift is=20
> 8.  signal tmp: std_logic_vector(7 downto 0);=20
> 9.  begin=20
> 10.    process (C)=20
> 11.      begin =20
> 12.        if (C'event and C=3D'1') then =20
> 13.         tmp <=3D tmp(6 downto 0)& SI;=20
> 14.        end if;=20
> 15.    end process;=20
> 16.    PO <=3D tmp;=20
> 17.end archi;=20
>=20
> Question:How does line 13 seem to do so much?

The "&" symbol in Line 13 is the concatenation operator. Line 13 performs t=
he shift by concatenating the lower 7 bits of the shift register with the s=
erial input, SI. This results in SI becoming bit 0 of tmp and bit 7 of tmp =
being discarded. Hope this helps.

Darol Klawetter

On 3/27/2015 7:22 PM, darol.klawetter@gmail.com wrote:
> On Friday, March 27, 2015 at 5:14:44 PM UTC-5, nobody wrote:
>> First, thank you for taking the time to consider the questions I have not answered.
>> I am working on a 32 bit serial to 32 bit parallel port which reads from an ADC. Currently looking to find a better solution, and I searched for predefined vhdl module with little success. I stumbled upon Macros, SR16CE, which utilize primitives but they seem to be schematic oriented and not available inside the ISE 8.2i, windows xp os.
>>
>> Question: Do common VHDL constructs exist in some library within the Xilinx folder file structure?
>>
>> Stumbling onto some help files within Xilinx website,http://www.csit-sun.pub.ro/courses/Masterat/Xilinx%20Synthesis%20Technology/toolbox.xilinx.com/docsan/xilinx4/data/docs/xst/hdlcode8.html, I found what I think I was looking for, however I need some help interpreting the VHDL statement that does everything, [line 13]:
>>
>> 8-bit Shift-Left Register with Positive-Edge Clock, Serial In, and Parallel Out
>> Note For this example XST will infer SRL16.
>>
>> 1.library ieee;
>> 2.use ieee.std_logic_1164.all;
>>
>> 3.entity shift is
>> 4. port(C, SI : in  std_logic;
>> 5.        PO : out std_logic_vector(7 downto 0));
>> 6.end shift;
>> 7.architecture archi of shift is
>> 8.  signal tmp: std_logic_vector(7 downto 0);
>> 9.  begin
>> 10.    process (C)
>> 11.      begin
>> 12.        if (C'event and C='1') then
>> 13.         tmp <= tmp(6 downto 0)& SI;
>> 14.        end if;
>> 15.    end process;
>> 16.    PO <= tmp;
>> 17.end archi;
>>
>> Question:How does line 13 seem to do so much?
>
> The "&" symbol in Line 13 is the concatenation operator. Line 13 performs the shift by concatenating the lower 7 bits of the shift register with the serial input, SI. This results in SI becoming bit 0 of tmp and bit 7 of tmp being discarded. Hope this helps.

Yes, that is a fairly straightforward expression of the shift function. 
  The question is whether your tool will be able to infer the use of two 
SRL16s.  Actually, I don't think an SRL16 is at all appropriate for a 
serial to parallel converter since it doesn't have a parallel output. 
The SRL16 is serial buffer, 1 bit in and 1 bit out.

If you look at the various sections on this page they list examples some 
of which say they *will* infer SRL16s and some say they *will not* infer 
SRL16s.  I think they made a mistake and left out the *not* for the 
section showing this code.  This is *not* Xilinx vetted info.  It is a 
third party source with unknown credentials.  I believe any of the code 
shown involving parallel input or output will not be inferred using SRL16s.

Look at this app note and I think you will see the limitation of the 
SRL16s.

http://www.xilinx.com/support/documentation/application_notes/xapp465.pdf

So the above code will work just fine.  It just won't, and in fact, 
*can't* use an SRL16.

Someone please correct me if I am wrong.

-- 

Rick

On Friday, March 27, 2015 at 7:23:57 PM UTC-7, rickman wrote:
> On 3/27/2015 7:22 PM, darol.klawetter@gmail.com wrote:
> > On Friday, March 27, 2015 at 5:14:44 PM UTC-5, nobody wrote:
> >> First, thank you for taking the time to consider the questions I have =
not answered.
> >> I am working on a 32 bit serial to 32 bit parallel port which reads fr=
om an ADC. Currently looking to find a better solution, and I searched for =
predefined vhdl module with little success. I stumbled upon Macros, SR16CE,=
 which utilize primitives but they seem to be schematic oriented and not av=
ailable inside the ISE 8.2i, windows xp os.
> >>
> >> Question: Do common VHDL constructs exist in some library within the X=
ilinx folder file structure?
> >>
> >> Stumbling onto some help files within Xilinx website,http://www.csit-s=
un.pub.ro/courses/Masterat/Xilinx%20Synthesis%20Technology/toolbox.xilinx.c=
om/docsan/xilinx4/data/docs/xst/hdlcode8.html, I found what I think I was l=
ooking for, however I need some help interpreting the VHDL statement that d=
oes everything, [line 13]:
> >>
> >> 8-bit Shift-Left Register with Positive-Edge Clock, Serial In, and Par=
allel Out
> >> Note For this example XST will infer SRL16.
> >>
> >> 1.library ieee;
> >> 2.use ieee.std_logic_1164.all;
> >>
> >> 3.entity shift is
> >> 4. port(C, SI : in  std_logic;
> >> 5.        PO : out std_logic_vector(7 downto 0));
> >> 6.end shift;
> >> 7.architecture archi of shift is
> >> 8.  signal tmp: std_logic_vector(7 downto 0);
> >> 9.  begin
> >> 10.    process (C)
> >> 11.      begin
> >> 12.        if (C'event and C=3D'1') then
> >> 13.         tmp <=3D tmp(6 downto 0)& SI;
> >> 14.        end if;
> >> 15.    end process;
> >> 16.    PO <=3D tmp;
> >> 17.end archi;
> >>
> >> Question:How does line 13 seem to do so much?
> >
> > The "&" symbol in Line 13 is the concatenation operator. Line 13 perfor=
ms the shift by concatenating the lower 7 bits of the shift register with t=
he serial input, SI. This results in SI becoming bit 0 of tmp and bit 7 of =
tmp being discarded. Hope this helps.
>=20
> Yes, that is a fairly straightforward expression of the shift function.=
=20
>   The question is whether your tool will be able to infer the use of two=
=20
> SRL16s.  Actually, I don't think an SRL16 is at all appropriate for a=20
> serial to parallel converter since it doesn't have a parallel output.=20
> The SRL16 is serial buffer, 1 bit in and 1 bit out.
>=20
> If you look at the various sections on this page they list examples some=
=20
> of which say they *will* infer SRL16s and some say they *will not* infer=
=20
> SRL16s.  I think they made a mistake and left out the *not* for the=20
> section showing this code.  This is *not* Xilinx vetted info.  It is a=20
> third party source with unknown credentials.  I believe any of the code=
=20
> shown involving parallel input or output will not be inferred using SRL16=
s.
>=20
> Look at this app note and I think you will see the limitation of the=20
> SRL16s.
>=20
> http://www.xilinx.com/support/documentation/application_notes/xapp465.pdf
>=20
> So the above code will work just fine.  It just won't, and in fact,=20
> *can't* use an SRL16.
>=20
> Someone please correct me if I am wrong.
>=20
> --=20
>=20
> Rick

Thank you for you time. I had similar thoughts having read xapp465. I guess=
 that still leaves me with needing a helpful solution toward utilizing a se=
rial to parallel hardware, which would seem very common and tucked away in =
some library somewhere. I came across the use of macros, but are based on g=
raphical symbols, schematics, and not VHDL. The macors seemed to be based o=
n the SR16CE but I have not been able to find hide nor hair of such a beast=
. Thank you!

On Monday, March 30, 2015 at 9:01:28 AM UTC-7, nobody wrote:
> On Friday, March 27, 2015 at 7:23:57 PM UTC-7, rickman wrote:
> > On 3/27/2015 7:22 PM, darol.klawetter@gmail.com wrote:
> > > On Friday, March 27, 2015 at 5:14:44 PM UTC-5, nobody wrote:
> > >> First, thank you for taking the time to consider the questions I hav=
e not answered.
> > >> I am working on a 32 bit serial to 32 bit parallel port which reads =
from an ADC. Currently looking to find a better solution, and I searched fo=
r predefined vhdl module with little success. I stumbled upon Macros, SR16C=
E, which utilize primitives but they seem to be schematic oriented and not =
available inside the ISE 8.2i, windows xp os.
> > >>
> > >> Question: Do common VHDL constructs exist in some library within the=
 Xilinx folder file structure?
> > >>
> > >> Stumbling onto some help files within Xilinx website,http://www.csit=
-sun.pub.ro/courses/Masterat/Xilinx%20Synthesis%20Technology/toolbox.xilinx=
.com/docsan/xilinx4/data/docs/xst/hdlcode8.html, I found what I think I was=
 looking for, however I need some help interpreting the VHDL statement that=
 does everything, [line 13]:
> > >>
> > >> 8-bit Shift-Left Register with Positive-Edge Clock, Serial In, and P=
arallel Out
> > >> Note For this example XST will infer SRL16.
> > >>
> > >> 1.library ieee;
> > >> 2.use ieee.std_logic_1164.all;
> > >>
> > >> 3.entity shift is
> > >> 4. port(C, SI : in  std_logic;
> > >> 5.        PO : out std_logic_vector(7 downto 0));
> > >> 6.end shift;
> > >> 7.architecture archi of shift is
> > >> 8.  signal tmp: std_logic_vector(7 downto 0);
> > >> 9.  begin
> > >> 10.    process (C)
> > >> 11.      begin
> > >> 12.        if (C'event and C=3D'1') then
> > >> 13.         tmp <=3D tmp(6 downto 0)& SI;
> > >> 14.        end if;
> > >> 15.    end process;
> > >> 16.    PO <=3D tmp;
> > >> 17.end archi;
> > >>
> > >> Question:How does line 13 seem to do so much?
> > >
> > > The "&" symbol in Line 13 is the concatenation operator. Line 13 perf=
orms the shift by concatenating the lower 7 bits of the shift register with=
 the serial input, SI. This results in SI becoming bit 0 of tmp and bit 7 o=
f tmp being discarded. Hope this helps.

Darol,

Thank you, that was helpful!

Cy

rickman <gnuarm@gmail.com> wrote:
> On 3/27/2015 7:22 PM, darol.klawetter@gmail.com wrote:
(snip)

>>> I am working on a 32 bit serial to 32 bit parallel port which 
>>> reads from an ADC.
(snip)

> Yes, that is a fairly straightforward expression of the shift function. 
>  The question is whether your tool will be able to infer the use of two 
> SRL16s.  Actually, I don't think an SRL16 is at all appropriate for a 
> serial to parallel converter since it doesn't have a parallel output. 
> The SRL16 is serial buffer, 1 bit in and 1 bit out.

Yes, but I think you can select which bit it is.

It will at least make constant length shift registers with lengths
other than 16.

The logic is similar to the usual LUT logic, but with the ability
to shift the bits in the LUT (RAM).
 
> If you look at the various sections on this page they list examples some 
> of which say they *will* infer SRL16s and some say they *will not* infer 
> SRL16s.  I think they made a mistake and left out the *not* for the 
> section showing this code.  This is *not* Xilinx vetted info.  It is a 
> third party source with unknown credentials.  I believe any of the code 
> shown involving parallel input or output will not be inferred using SRL16s.

I am not so good at figuring out Xilinx primitives, but I did figure
out how to use a clock generator as a Xilinx primitive.

I think you should be able to generate a shift register, counter, and
multiplexer, to shift and then select which bit to send out.
It might take primitives to do that, though.

-- glen

On 3/30/2015 12:01 PM, nobody wrote:
> On Friday, March 27, 2015 at 7:23:57 PM UTC-7, rickman wrote:
>> On 3/27/2015 7:22 PM, darol.klawetter@gmail.com wrote:
>>> On Friday, March 27, 2015 at 5:14:44 PM UTC-5, nobody wrote:
>>>> First, thank you for taking the time to consider the questions I have not answered.
>>>> I am working on a 32 bit serial to 32 bit parallel port which reads from an ADC. Currently looking to find a better solution, and I searched for predefined vhdl module with little success. I stumbled upon Macros, SR16CE, which utilize primitives but they seem to be schematic oriented and not available inside the ISE 8.2i, windows xp os.
>>>>
>>>> Question: Do common VHDL constructs exist in some library within the Xilinx folder file structure?
>>>>
>>>> Stumbling onto some help files within Xilinx website,http://www.csit-sun.pub.ro/courses/Masterat/Xilinx%20Synthesis%20Technology/toolbox.xilinx.com/docsan/xilinx4/data/docs/xst/hdlcode8.html, I found what I think I was looking for, however I need some help interpreting the VHDL statement that does everything, [line 13]:
>>>>
>>>> 8-bit Shift-Left Register with Positive-Edge Clock, Serial In, and Parallel Out
>>>> Note For this example XST will infer SRL16.
>>>>
>>>> 1.library ieee;
>>>> 2.use ieee.std_logic_1164.all;
>>>>
>>>> 3.entity shift is
>>>> 4. port(C, SI : in  std_logic;
>>>> 5.        PO : out std_logic_vector(7 downto 0));
>>>> 6.end shift;
>>>> 7.architecture archi of shift is
>>>> 8.  signal tmp: std_logic_vector(7 downto 0);
>>>> 9.  begin
>>>> 10.    process (C)
>>>> 11.      begin
>>>> 12.        if (C'event and C='1') then
>>>> 13.         tmp <= tmp(6 downto 0)& SI;
>>>> 14.        end if;
>>>> 15.    end process;
>>>> 16.    PO <= tmp;
>>>> 17.end archi;
>>>>
>>>> Question:How does line 13 seem to do so much?
>>>
>>> The "&" symbol in Line 13 is the concatenation operator. Line 13 performs the shift by concatenating the lower 7 bits of the shift register with the serial input, SI. This results in SI becoming bit 0 of tmp and bit 7 of tmp being discarded. Hope this helps.
>>
>> Yes, that is a fairly straightforward expression of the shift function.
>>    The question is whether your tool will be able to infer the use of two
>> SRL16s.  Actually, I don't think an SRL16 is at all appropriate for a
>> serial to parallel converter since it doesn't have a parallel output.
>> The SRL16 is serial buffer, 1 bit in and 1 bit out.
>>
>> If you look at the various sections on this page they list examples some
>> of which say they *will* infer SRL16s and some say they *will not* infer
>> SRL16s.  I think they made a mistake and left out the *not* for the
>> section showing this code.  This is *not* Xilinx vetted info.  It is a
>> third party source with unknown credentials.  I believe any of the code
>> shown involving parallel input or output will not be inferred using SRL16s.
>>
>> Look at this app note and I think you will see the limitation of the
>> SRL16s.
>>
>> http://www.xilinx.com/support/documentation/application_notes/xapp465.pdf
>>
>> So the above code will work just fine.  It just won't, and in fact,
>> *can't* use an SRL16.
>>
>> Someone please correct me if I am wrong.
>>
>> --
>>
>> Rick
>
> Thank you for you time. I had similar thoughts having read xapp465. I guess that still leaves me with needing a helpful solution toward utilizing a serial to parallel hardware, which would seem very common and tucked away in some library somewhere. I came across the use of macros, but are based on graphical symbols, schematics, and not VHDL. The macors seemed to be based on the SR16CE but I have not been able to find hide nor hair of such a beast.. Thank you!


I'm not sure what you are trying to do.  The code you have above will do 
the job of a serial to parallel shift register.  Why do you need to 
worry about which primitives get used in the FPGA?

-- 

Rick