ML403 board - VGA schematics - wrong pins

Hi,

I am trying to do my own vga driver for ML403 board. I have done the
same vga driver for other boards, so I only have to change the FPGA
pins labels.

I was looking for the pins in ML403 board in the schematics provided by
xilinx and when I tried to map my design I got:

ERROR:MapLib:30 - LOC constraint M24 on PIN_M24 is invalid: No such
site on the ...
ERROR:MapLib:30 - LOC constraint L23 on PIN_L23 is invalid: No such
site on the ...

I understand that this pins labels are invalid in the FPGA of ML403
board, and when I look for the pins in the Virtex IV datasheet I see
that this both pins are not connected in the xc4vfx12ff668-10 FPGA.

So I think that the information provided by is wrong, anybody know how
can I get the right pins?

The BLUEpins, GREENpins, REDpins, VSYNCpin, HSYNCpin and CLOCKpin are
right the wrong are:

BLANKpin  "M24"
SYNCpin "L23"

Thanks in advance

Gerardo Sosa

On 24 Jan 2007 11:41:42 -0800, gsosar@gmail.com wrote:

>ERROR:MapLib:30 - LOC constraint L23 on PIN_L23 is invalid: No such
>site on the ...
>
>I understand that this pins labels are invalid in the FPGA of ML403
>board, and when I look for the pins in the Virtex IV datasheet I see
>that this both pins are not connected in the xc4vfx12ff668-10 FPGA.

>The BLUEpins, GREENpins, REDpins, VSYNCpin, HSYNCpin and CLOCKpin are
>right the wrong are:
>
>BLANKpin  "M24"
>SYNCpin "L23"
>
>Thanks in advance
>
>Gerardo Sosa

Hi, namesake,

On the ML403, some VGA pins are missing, IIRC there are only 5 bits per colour.
On the ML402, these pins are available. The epoxy board seems to be the same.
(I have ML402s only)

The 3 bits are not much of a loss, because the analog quality of the DAC
outputs is so sh***y that you will never see pretty eye diagrams etc if you use them 
as pseudo-analog test points for your DSP stuff (clock feedthru, overshoot...)
That hurts, because the ML402 is meant for DSP.

BTW, will the Webpack 9.1 recognize a valid full ISE 8.1 installation and work for the V4-SX35
on the ML402? (interim solution until the CDs are here)

regards, Gerhard

Hi Gerardo Sosa

I switch from ML402 to ML403 and back quite often.
The ML403 give me faster compile times so it's good
for testing small designs. When I do this I comment
the extra pins out as shown in the UCF file below.

I also have to change my VHDL to reflect fewer
inputs with the ML403 and I am searching for a
way to automate that procedure.

It seems like I don't use the blank, sync_n,
or p_save pins in either design.
Just HSYNC VSYNC and CLK. They must be pulled
to acceptable levels.

Brad Smallridge
AiVision


# VGA OUTPUTS

NET "vga_clk_out"    LOC = "AF8" ;
NET "vga_clk_out"    IOSTANDARD = LVDCI_33 ;
NET "vga_clk_out"    SLEW = FAST ;
NET "vga_clk_out"    DRIVE = 8 ;

NET "vga_vsync_out"  LOC = "A8" ;
NET "vga_vsync_out"  SLEW = FAST ;
NET "vga_vsync_out"  DRIVE = 8 ;

NET "vga_hsync_out"  LOC = "C10" ;
NET "vga_hsync_out"  SLEW = FAST ;
NET "vga_hsync_out"  DRIVE = 8 ;

NET "vga_b_out<3>"  LOC = "C5"  ; # VGA_B3 or tft_lcd_b<1>
NET "vga_b_out<4>"  LOC = "C7"  ; # VGA_B4 or tft_lcd_b<2>
NET "vga_b_out<5>"  LOC = "B7"  ; # VGA_B5 or tft_lcd_b<3>
NET "vga_b_out<6>"  LOC = "G8"  ; # VGA_B6 or tft_lcd_b<4>
NET "vga_b_out<7>"  LOC = "F8"  ; # VGA_B7 or tft_lcd_b<5>
#NET vga_b_out<*> IOSTANDARD = LVCMOS33;
NET "vga_g_out<3>"  LOC = "E4"  ; # VGA_G3 or tft_lcd_g<1>
NET "vga_g_out<4>"  LOC = "D3"  ; # VGA_G4 or tft_lcd_g<2>
NET "vga_g_out<5>"  LOC = "H7"  ; # VGA_G5 or tft_lcd_g<3>
NET "vga_g_out<6>"  LOC = "H8"  ; # VGA_G6 or tft_lcd_g<4>
NET "vga_g_out<7>"  LOC = "C1"  ; # VGA_G7 or tft_lcd_g<5>
#NET vga_g_out<*> IOSTANDARD = LVCMOS33;
NET "vga_r_out<3>"  LOC = "C2"  ; #VGA_R3 tft_lcd_r<1>
NET "vga_r_out<4>"  LOC = "G7"  ; #VGA_R4 tft_lcd_r<2>
NET "vga_r_out<5>"  LOC = "F7"  ; #VGA_R5 tft_lcd_r<3>
NET "vga_r_out<6>"  LOC = "E5"  ; #VGA_R6 tft_lcd_r<4>
NET "vga_r_out<7>"  LOC = "E6"  ; #VGA_R7 tft_lcd_r<5>

# extra VGA connections for ML402 not ML403
#NET vga_b_out<0> LOC = "M26";
#NET vga_b_out<1> LOC = "M21";
#NET vga_b_out<2> LOC = "L26";
#NET vga_g_out<0> LOC = "M22";
#NET vga_g_out<1> LOC = "M23";
#NET vga_g_out<2> LOC = "M20";
#NET vga_r_out<0> LOC = "N23";
#NET vga_r_out<1> LOC = "N24";
#NET vga_r_out<2> LOC = "N25";
# END EXTRA CONNECTIONS

#NET vga_psave_n LOC = "M25";
#NET vga_blank_n LOC = "M24";
#NET vga_sync_n LOC =  "L23";

# drive strength and speed for VGA
NET vga_r_out<*> SLEW  = FAST;
NET vga_r_out<*> DRIVE = 8;
NET vga_g_out<*> SLEW  = FAST;
NET vga_g_out<*> DRIVE = 8;
NET vga_b_out<*> SLEW  = FAST;
NET vga_b_out<*> DRIVE = 8;

Thanks por the advice, I'm going to modify my ADV7125 driver to work
with HSYNC VSYNC and CLK signals only.

Regards

Gerardo

Thanks Brad...It's works!!!

I removed the code for Blank and Sync lines and force the rgb channels
to black in the front porch, sync pulse and back porch.

In my original driver it's no matter the data in rgb channels, because
Blank and sync lines force the blanking.

Thank you very much for the advice, I solved in less than five minutes.

Regards 

Gerardo Sosa

On Friday, January 26, 2007 at 12:34:59 AM UTC+6, gso...@gmail.com wrote:
> Thanks por the advice, I'm going to modify my ADV7125 driver to work
> with HSYNC VSYNC and CLK signals only.
> 
> Regards
> 
> Gerardo

I use ML405 did same things for my board but there is not success, can you explain what are these things means , may be i need to change something to adopt to my board ?

On Mon, 23 Nov 2015 03:44:50 -0800, abirov wrote:

> On Friday, January 26, 2007 at 12:34:59 AM UTC+6, gso...@gmail.com
> wrote:
>> Thanks por the advice, I'm going to modify my ADV7125 driver to work
>> with HSYNC VSYNC and CLK signals only.
>> 
>> Regards
>> 
>> Gerardo
> 
> I use ML405 did same things for my board but there is not success, can
> you explain what are these things means , may be i need to change
> something to adopt to my board ?

That post is nearly 9 years old, so he has probably forgotten by now.

-- Brian

On Monday, November 23, 2015 at 5:48:25 PM UTC+6, Brian Drummond wrote:
> On Mon, 23 Nov 2015 03:44:50 -0800, abirov wrote:
> 
> > On Friday, January 26, 2007 at 12:34:59 AM UTC+6, gso...@gmail.com
> > wrote:
> >> Thanks por the advice, I'm going to modify my ADV7125 driver to work
> >> with HSYNC VSYNC and CLK signals only.
> >> 
> >> Regards
> >> 
> >> Gerardo
> > 
> > I use ML405 did same things for my board but there is not success, can
> > you explain what are these things means , may be i need to change
> > something to adopt to my board ?
> 
> That post is nearly 9 years old, so he has probably forgotten by now.
> 
> -- Brian

Yep ))))