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Comp.Arch.FPGA
Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.
There are 16332 threads in our archives.
You are looking at page 10 of 1634.
The threads with the newest articles are listed first.
Progrmming a flash connected to a Stratix II GX [2 articles]
jfh - 2010-02-09 05:02:00
Hi;
We are trying to program a CFI Flash (Numonyx TE28F320J3D75) using the
flash programmer of Quartus II/EDS 9.1. We followed the instructions
given in the User's Guide (from february 2010 !), ...
different JTAG programming cables [4 articles]
David Fejes - 2010-02-08 09:26:00
Hello guys,
is there any chance to get work a lattice jtag programming cable with
xilinx products? I think, JTAG is a common standard, didn't? I've a hw-
usbn-2a lattice cable and I want use with...Matching hadware and software CRC [7 articles]
dlopez - 2010-02-08 03:33:00
Hi,
There seems to be an endless numbers of way to mess up CRC calculations!
Has anyone come up with the right way to match a software calculated CRC
with whay comes out of either the 'easics' core o...Simulating Spartan 3A pins in ltspice [14 articles]
Patrick Maupin - 2010-02-08 01:10:00
Xilinx claims:
We recommend the use of IBIS models whenever possible. IBIS models for
many devices are often available as free downloads. Using IBIS
provides the following:
* Faster simula...Databus crossing clock domains with data freeze [17 articles]
Nicholas Kinar - 2010-02-07 09:45:00
Hello--
What is the best standard practice to have a data bus cross a clock
domain by implementing a data freeze?
There is an extremely brief description of the data freeze given here:
http:/...Constraining minimum hold times (Xilinx) [11 articles]
Uwe Bonnes - 2010-02-06 13:32:00
Hello,
is there a way to constrain minimum hold time requirements with ISE?
I am trying to write to an FT2232H in synchronous FIFO mode. The FT2232H
supplies a 60 MHz clock and specifies 11 ns ...How good are Actel tools [6 articles]
rickman - 2010-02-05 13:00:00
I know Antti has a lot of experience with Actel, so I expect to hear
from him, but I am sure there are others out there with experience of
Actel tools. A customer of mine has told me that he used A...ISPLever, devlist command
jbj - 2010-02-05 11:03:00
Hello,
i use ISPLever 7.1 - 8.0, but I have a major trouble :
When I try to launch devlist -l command in the ISPLever console, the result
is empty.
BUT this command should return the list of...Issue with Altera flash programmer [2 articles]
Pascal_Olive - 2010-02-04 23:43:00
Hello,
I have a design based on a EP2SGX30 FPGA, with a CFI Flash connected
to it, in order to store the functional program.
I'm trying in vain to program this Flash (Numonyx TE28F320J3D75) usi...Quartus II - Generating Verilog from MegaWizard plugins
Giorgos Tzampanakis - 2010-02-04 16:16:00
I'm using the MegaWizard plugin manager on Quartus II 9.1 on linux and I
can't get it to generate any Verilog files for me. It does generate VHDL
files. There is an option to generate Verilog but it...