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Comp.Arch.FPGA


Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.

There are 16714 threads in our archives.

You are looking at page 10 of 1672.

The threads with the newest articles are listed first.

Xilinx License BS [4 articles]

M.Randelzhofer - 2010-07-20 04:49:00
Tried to install ISE 12.x Webpack for supporting a customer. After 6 hours of downloading, installing and cleaning up HDD space i made a small mistake in the first install process to obtain a licen...Xilinx License BS

I2C Master Start stop generation [6 articles]

Vips - 2010-07-19 12:26:00
Hi All I am implementing an I2C slave and low level interface to interface it to EEPROM. I am using I2c Master for verifying this module . The I2C Master code is reused from some other module. He...I2C Master Start stop generation

Another Xilinx webpack download rant [13 articles]

Nicolas Matringe - 2010-07-19 10:13:00
Hello I've been trying to download these 2.9GB for 3 days with numerous retries (thanks to the download manager, the 'resume' resulted in a restart from 0) and when I finally managed to get the ful...Another Xilinx webpack download rant

Virtex 4 FX12 minimodule

bhatti - 2010-07-19 07:10:00
Hi all Has any one used Virtex 4 FX12 minimodule along with any ADC(analog to digital converter) IC for sending digitiized data on ethernet? If someone has any experience on FX12 mini module kin...Virtex 4 FX12 minimodule

HDL float to string (sprintf %.3E)? [3 articles]

John Speth - 2010-07-17 06:28:00
Hi folks- I've asked this question on various FPGA formums so please excuse my persistence. I'm hoping different eyes might see my question and be able to help. I'm looking for an HDL repla...HDL float to string (sprintf %.3E)?

WTD: WISHBONE SDRAM interface or some Vlog HDL synthesizing... [5 articles]

Philip Pemberton - 2010-07-17 06:24:00
Hi guys, I'm (still) trying to chase down an issue with the SDRAM on an Enterpoint Drigmorn2 development board. Basically, the SDRAM is acting like the mythical Write Only Memory -- I can write...WTD: WISHBONE SDRAM interface or some Vlog HDL synthesizing...

Drigmorn4 - Spartan-6 Board [2 articles]

John Adair - 2010-07-16 20:17:00
Our third product based on Spartan-6 is Drigmorn4 http://www.enterpoint.co.uk/drigmorn/drigmorn4.html and it is now available in very limited quantities. It's very much of the same concept as Drigm...Drigmorn4 - Spartan-6 Board

help regarding daisy chained fpgas [6 articles]

salimbaba - 2010-07-16 09:25:00
Hello! I am using xcf16p EEPROM, and 2 xc3s4000 FPGAs connected in a daisy chain on a custom board. The problem is when i program my FPGAs through JTAG interface, FPGA 1 always gets programmed and ve...help regarding daisy chained fpgas

Timing analysis of asynchronous bus peripherals

primiano - 2010-07-16 06:40:00
Hello everyone, I have a (maybe) simple problem I don't know exactly how to face up. I am given a design (which is made by a third person) that realizes simple bus peripherals upon a Altera CPLD. ...Timing analysis of asynchronous bus peripherals

1-wire question [2 articles]

Giuseppe Marullo - 2010-07-16 01:49:00
HI all, I would like to write a decoder for 1-wire but I am stuck about the search algorithm. My question is: is it possible for a third party, without knowing the 1-Wire master and "slave" st...1-wire question
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