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Comp.Arch.FPGA


Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.

There are 17402 threads in our archives.

You are looking at page 10 of 1741.

The threads with the newest articles are listed first.

high speed place and route about xilinx [4 articles]

bjzhangwn@gmail.com - 2011-10-10 12:38:00
Now I am troubled that I must wait several hours to compile large circuits,and the place and route result is different from each time,for example the p&r time for this time is may be 2hrs and may b...high speed place and route about xilinx

MAXDELAY constraint [8 articles]

Andrew Holme - 2011-10-09 08:19:00
I have a 200 MHz clock gated by a BUFGMUX. I added some unrelated logic and the routing of the gate control signal got longer and broke the FPGA. The routing delay in earlier versions was ~ 1.8n...MAXDELAY constraint

Is it possible to use a remote desktop viewer on NIOS Linux

Ahmed Abdelfattah - 2011-10-08 11:34:00
Hello , I am having a project where I need to take control of a pc or a smart phone which has a VNC server using FPGA so I need to run a client from the FPGA side . Is this possible ? My kit is th...Is it possible to use a remote desktop viewer on NIOS Linux

VHDL connection problem [4 articles]

maxascent - 2011-10-06 06:36:00
I have a memory that output a 64-bit slv. I have another module that has a record type with a data 64-bit slv input. I want to connect the two together. If I do this I get x. If I disconnect them the ...VHDL connection problem

Spartan-6 PCI speed

Finn S. Nielsen - 2011-10-05 09:54:00
Hello all, Has anyone used XAPP1052 for testing the speed of the PCI hard macro in the spartan-6 LXT FPGAs ? What speeds are you getting ? Regards, Finn S. Nielsen Morphologic ApS www....Spartan-6 PCI speed

Testbench [5 articles]

maxascent - 2011-10-05 08:48:00
I would like to write a testbench in VHDL using constrained random values and transactions. Are there any free packages that people know about that do this sort of thing? TIA ------...Testbench

macro [3 articles]

molka - 2011-10-05 03:02:00
Hello everybody, I need help in dealling with hard macros (in vhdl). I want to instantiate my macro in a vhdl design. any one have an idea how to do it ? I tied to do as instantiating vhdl mod...macro

FPGA acceleration v.s. GPU acceleration [7 articles]

vcar - 2011-10-04 14:11:00
I was an FPGA engineer before and I think high performance computing based FPGA will lead to a bright future. However through my recently projects I found GPU will be more appropriate when there is ...FPGA acceleration v.s. GPU acceleration

most stable version of ISE ? [4 articles]

Mike Harrison - 2011-10-03 13:51:00
I've seen lots of messages a while ago about how ISE is going downhill... Which version of ISE would people recommend for fairly simple VHDL projects using Spartan-3 and Spartan-6? I'm currently ...most stable version of ISE ?

ISE 13.2 CPLD Schematic projects

2011-10-03 11:43:00
Could someone please try the following: In ISE 13.2, open one of the 9572XL schematic example projects (jc2_sch, jc2_sver or jc2_svhd) and run the Floorplan IO - Pre-Synthesis process. Does the...ISE 13.2 CPLD Schematic projects
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