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Comp.Arch.FPGA
Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.
There are 16329 threads in our archives.
You are looking at page 11 of 1633.
The threads with the newest articles are listed first.
Xilinx ISE 8.2 Issue: Pin Name N1, N2... [3 articles]
moogyd - 2010-02-04 09:18:00
Hello,
I am seeing a problem using ISE. I have a verilog top level with pins
including N0, N1, N2, N3, N4 (similar for PX, SX and MX)
I add a LOC constraint in the UCF file for all pins. For so...
synthesizing a completely empty design for an FPGA to measure quiescent current [22 articles]
EE EE - 2010-02-04 06:10:00
Hi
I want to synthesize a completely empty design, no clocks no combo and
no sequential logic for a xilinx FPGA using ISE.
THe problem is
if I try to implement module dummy_fpga (); endmodule
Th...Help Please - Xilinx message [8 articles]
Daku - 2010-02-04 04:57:00
Could some Xilinx guru please help ? I have the following module
synthesized on Xilinix ISE 11.1. I am getting a message at the end of
synthesis that no clock exists for design - could some please k...Draft paper submission deadline is extended: HPCS-10
James Heralds - 2010-02-03 17:08:00
Draft paper submission deadline is extended: HPCS-10
The 2010 International Conference on High Performance Computing
Systems (HPCS-10) (website: http://www.PromoteResearch.org) will be
held duri...Unknown LVDS pinout order
jorbedo - 2010-02-03 06:25:00
Hi, I had been learning LVDS as a hobby but I'm having a hard time
understanding the pinout orders.
Right know I would like to know the precise order of the pinouts of an LCD
panel (30 pin I-Pex co...Spartan 3 configuration [2 articles]
gopal_amlekar - 2010-02-03 05:15:00
Hello,
Few days back, I got a good help from this forum about CPLD programming.
I have succeded in making my own design based on a microcontroller to
configure a spartan 2 as well as to program XC...What MAXIM chip is used on Spartan 3E 1600E Microblaze Board for RS232 communication? [13 articles]
Alex - 2010-02-03 04:14:00
Hello All,
I have started using Xilinx Spartan3E 1600E Microblaze Development
Board and want to use its RS232 facility in my project. This board has
two RS232 connectors but I cannot figure out w...vhdl divider [4 articles]
zanaticul - 2010-02-02 06:42:00
Hello,
i want to split a number for example 1234 in 4 numbers 1,2,3,4
witch is the best way to do it?
i was thinking of using this code
tmp := number;
o4 := number mod 10;
tmp :...Single Port Rom created by Core Generator configurable by generic values!!!! [9 articles]
bellatoise - 2010-02-02 04:01:00
Hi,
My query is the next:
I'm working with Xilinx Ise Design Suite 11.1.
I need some ROMS with differents values of depth, width and initialization
files that I want to instantiate in one proyect...In system memory editor of Altera for Xilinx [34 articles]
jmunir - 2010-02-02 03:58:00
Hi!,
I have been working with Altera FPGAs for a long time and now I have to
deal with Xilinx ones. Until now, with Quartus II I have been able to
manage the content of different registers and memo...