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Comp.Arch.FPGA


Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.

There are 16714 threads in our archives.

You are looking at page 12 of 1672.

The threads with the newest articles are listed first.

LXT972 pass-through packet

leoeltipo - 2010-07-07 06:19:00
Hello. I have designed an ethernet interface with a Xilinx Virtex 5 FPGA and a LXT972 Intel's IC. Besides, I have a GUI designed in the computer host to send/receive files and information. Using a...LXT972 pass-through packet

spartan 3xc3s4000 daisy chain help required [4 articles]

salimbaba - 2010-07-07 01:28:00
Hi, I am using spartan 3 FPGAs and 1 EEPROM XCF16P in daisy chain configuration and programming it through JTAG but i am getting this error continuously " DONE did not go high".The TDI of JTAG is ...spartan 3xc3s4000 daisy chain help required

6 kbytes BRAM and Xst:2260 [2 articles]

aleksa - 2010-07-06 22:30:00
I'm using Coregen on XC2S200 to generate a 6144 bytes (12 blocks) BRAM and I get these infos: INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches : ...6 kbytes BRAM and Xst:2260

Difference between DDR and DDR2 [5 articles]

Fred - 2010-07-06 06:41:00
I'm trying to see the difference from an external point of view, and I can't see one, apart from having a 1.8V supply rather than a 2.5V. I can see increased clock speed and increased clock latenc...Difference between DDR and DDR2

Q: Standard Programming Idiom [3 articles]

Richard - 2010-07-06 03:06:00
Hi all, I just came across a - what I think - must be a quite standard programming idiom for implementing an FSM. Essentially, I read a byte value byte_in sequentially, and assign it to the appr...Q: Standard Programming Idiom

software for xc3000 [3 articles]

Krzych - 2010-07-05 14:53:00
I'm looking for Xilinx Foundation 3.1i or XACT 5 or 6 because I want to use XC3000 FPGA. I know, that chips are very old but I don't want scrap it. Maybe someone has copy? Thanks Krzych ...software for xc3000

SPI Flash configuration and data access rate [6 articles]

Gladys - 2010-07-05 06:57:00
Hi, I'm implementing an FPGA prototype to do some image processing such as dead pixel correction. The xilinx FPGA will be configured with an SPI flash memory,where the .bit configuration file inside...SPI Flash configuration and data access rate

fooling the compiler [23 articles]

John Larkin - 2010-07-03 13:46:00
We have a Spartan6/45 that's talking to 16 separate SPI A/D converters. The data we get back is different, but the clock and chip select timings are the same. To get the timing right, avoiding r...fooling the compiler

carrier tracking over zero frequency point [4 articles]

kadhiem_ayob - 2010-07-03 13:03:00
Hi All, I am developing a carrier tracking module for 16QAM receiver based on Costas loop on an fpga platform. Tracking works well on either side of zero frequency and over zero if crossing rate is...carrier tracking over zero frequency point

Xilinx xapp175, empty + full flag really synchronous? [10 articles]

firefox3107 - 2010-07-02 14:34:00
Hey, I found an amazing async fifo concept on the xilinx homepage. It looks that the latency to share data between clock domains is reduced to one cycle. But I'm asking if the setup + hold times...Xilinx xapp175, empty + full flag really synchronous?
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