Sign in

username:

password:



Not a member?

Search Comp.Arch.FPGA



Search tips

fpga by Keywords

Altera | ASIC | CPLD | Cyclone | DCM | DDR | DSP | Ethernet | ISE | JTAG | Linux | LVDS | Microblaze | ML310 | Modelsim | NIOS | OPB | PCI | Quartus | RocketIO | SDRAM | Spartan | Spartan3 | SRAM | Stratix | Verilog | VHDL | Virtex | Virtex-4 | Virtex-II | Xilinx | XST

Ads

See Also

DSPEmbedded SystemsElectronics

Comp.Arch.FPGA

Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.

There are 17402 threads in our archives.

You are looking at page 12 of 1741.

The threads with the newest articles are listed first.

Registers at I/O [8 articles]

valtih1978 - 2011-09-25 13:57:00
Synthesis optimization people seem to like registers at I/O. Particularly, in Xilinx manual: "The synthesis tools will not optimize across the Partition interface. If an asynchronous timing ...Registers at I/O

Job offer for ALTERA FPGA electronic engineer developper

Jose Miguel - 2011-09-25 11:00:00
Interested people contact me. The skill: Electronic engineer, TI engineer, Phisics BS or PhD, expert in FPGA design and digital and analog circuits design. Inmediate incorporation. Work in S...Job offer for ALTERA FPGA electronic engineer developper

Minimalist Spartan6-LX150 Board for $250

Lamont Cranston - 2011-09-24 17:59:00
This may be of interest to comp.arch.fpga: https://bitcointalk.org/index.php?topic=45532.msg543312 ...Minimalist Spartan6-LX150 Board for $250

Browser-Based Timing Diagram Editor [3 articles]

Kevin Neilson - 2011-09-23 07:01:00
I used to use a really nice, simple, browser-based timing diagram editor, and now I've forgotten the name and URL of this tool. Does anybody know which one I'm talking about? There was a text wind...Browser-Based Timing Diagram Editor

gigabit ethernet problem

salimbaba - 2011-09-22 15:21:00
Hi, I am using xilinx spartan3 xc3s4000 in my design. It is interfaced with 2 national Gigabit PHYs. So i receive a packet from phy A and transmit it to PHY B and vice versa. Now the problem i am fac...gigabit ethernet problem

Xilinx Spartan-3 Starter Kit and Webpack 13.2 [3 articles]

alekceywk - 2011-09-22 01:41:00
Hello all, I'm just starting into FPGA's, and have access to a Spartan-3 Starter board. Even though it dates back to 2004 and is no longer supported by Xilinx, I expect I should be able to at le...Xilinx Spartan-3 Starter Kit and Webpack 13.2

SIM card 1.8V / 3V sensing [3 articles]

Mike Perkins - 2011-09-20 05:32:00
Can anyone steer me in the right direction of an article how one is meant to determine if a SIM card is of the 1.8V, or the 3V variety? Many thanks in advance. -- Mike Perkins Video Solut...SIM card 1.8V / 3V sensing

Virtex 6 dev. board suppliers? [7 articles]

rupertlssmith@googlemail.com - 2011-09-19 14:11:00
Hi, I'm looking for a Xilinx Virtex 6 based dev. board, (with PCIe and SFP connectors for 10G Ethernet). Other than Hitech Global, what other suppliers are there? You suggestions are much appreci...Virtex 6 dev. board suppliers?

Has anybody used IOB_DLY_ADJ with S(2:0) input? [2 articles]

Svenn Are Bjerkem - 2011-09-19 09:29:00
Hi, I have a DDR input which every now and then gives me a nonfunctional implem= entation due to unlucky input data clocking. Thought I would try to use the= variable delay input elements with the...Has anybody used IOB_DLY_ADJ with S(2:0) input?

How to digitize the VGA output using FPGA? [6 articles]

Test01 - 2011-09-19 04:02:00
I would like to know if there is a development kit and documentation available to digitize the VGA siganls to create the a digital video fram using FPGA. I see lot of fpga applications that gener...How to digitize the VGA output using FPGA?
previous | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | next