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Comp.Arch.FPGA
Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.
There are 16329 threads in our archives.
You are looking at page 12 of 1633.
The threads with the newest articles are listed first.
How can I convert size requirements from Altera devices to Xilinx devices? [4 articles]
Sam - 2010-02-01 22:32:00
I have two designs for an Altera chip that use approximately 6,000 and
24,000 logic elements. I am looking at moving to Xilinx tools, but am
not sure how these numbers translate across manufacturers...
Connecting ADC chip to sparta 3 a dsp [3 articles]
lakshmi3489 - 2010-02-01 22:02:00
hi there
I have an ADC chip which is working in the LVDS mode.
The data out(D0+,D0-,......D13+ and D13-),along with data clock
out(DC0+,DC0-)
and out of range(OUR) are connected physically to...DPA vs FPGA Security? [14 articles]
emeb - 2010-02-01 12:31:00
Just read an article over at FPGA Journal about ways to bypass the
security features on FPGA designs:
http://www.techfocusmedia.net/fpgajournal/feature_articles/20100126-fending/
A lot of scary...offset constrain report confusion [7 articles]
realwood - 2010-02-01 09:48:00
Hi, everybody:
I'm confused with offset constraint and its report recently. Can anyone
help me? Thanks very much!
"din" is a input data whose bus width is 32bit. I set a offset
constraint...Quartus Web Edition on Linux - no simulation? [2 articles]
Giorgos Tzampanakis - 2010-01-31 12:58:00
I just installed Quartus II Web Edition 9.1 on linux. I compiled a simple
test project and only then I noticed that simulation is unsupported! It's
supported on the Windows version, so how come this...Xilinx DCM: Is CLKIN_PERIOD really required [5 articles]
Sudhir Singh - 2010-01-30 05:52:00
Hi Guys,
Just wondering if the CLKIN_PERIOD value needs to be set to the period
of input clock when instantiating a DCM component. I have a design
where input clock can be either 25MHz or 125MHz,...E1 clock problem with Spartan3e... [8 articles]
Morppheu - 2010-01-29 15:19:00
Hey guys...
I need a little help with my E1 interface.
I have an internal clock and the E1 clock. When E1 chip (MT9076B) is
present I use the E1 clock + E1 F0 signals, else I use the internal
cl...usb transfer between PC and de2 board
summer - 2010-01-29 12:28:00
hi everyone,
I need to transfer 16 bytes data block (a packet of 16 bytes data) from PC
to DE2 board and then the DE2 board will send the data back to PC.
I’m use the firmware of device contro...timing properties of fpga devices at sub-clock frequencies [15 articles]
Pallavi - 2010-01-29 03:54:00
Hello,
I need to implement a project as a part of my Masters curriculum using fpga
devices that would generate delays, that is generate higher output
frequencies than the system clock using propaga...Thank you, SunMicrosystem [4 articles]
Weng Tianxiang - 2010-01-28 15:33:00
Hi,
Sun Microsystem provides a full set of valuable resource on its
webside: http://www.opensparc.net/opensparc-t2/download.html
I printed all its documents and books about 2K pages free.
I th...