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Comp.Arch.FPGA

Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.

There are 17402 threads in our archives.

You are looking at page 13 of 1741.

The threads with the newest articles are listed first.

clock enable for fixed interval [8 articles]

Jim - 2011-09-19 01:48:00
What would be the proper way to clock a register at a fixed multiple of the system clock? I am trying to create a signal that is active around the rising edge of the system clock as a clock enable....clock enable for fixed interval

LFSR in xilinx 13.2 [5 articles]

salimbaba - 2011-09-16 08:35:00
Hi, I am using xilinx 13.2 for my design synthesis and i want to use xilinx IP for LFSR but i cannot find it in core gen. I am using Spartan3 xc3s4000 FPGA. Does anyone know where i can find it? ...LFSR in xilinx 13.2

reduce EDK synthesis time [5 articles]

catto - 2011-09-15 11:26:00
Hello, i'm working on microblaze project (using ISE 10.1) and obviously adding peripheral the EDK synthesis takes a long time. There's a method or tool to improve this time?? I've tried the -smart...reduce EDK synthesis time

CONSTRAINTS [2 articles]

varun_agr - 2011-09-15 05:32:00
Sir When we run our vhdl programme it sysnthesize and implemented witout any error, In place and route report it gives as: Generating Clock Report ************************** +----------------...CONSTRAINTS

Lattice XP2 getting hot and/or reading 0's as JTAG ID [7 articles]

Antti - 2011-09-12 11:19:00
Hi I guess I am alone with the issue, but asking still :) board(s) working ok, FPGA in SDM mode. suddenly after some repramming FPGA 1) goes HOT, reads bad JTAG ID, can be restored to live b...Lattice XP2 getting hot and/or reading 0's as JTAG ID

interfacing Xilinx platform usb jtag with other vendor devices [4 articles]

salimbaba - 2011-09-09 11:57:00
is xilinx platform usb jtag supports non-xilinx devices regards salim --------------------------------------- Posted through http://www.FPGARelated.com ...interfacing Xilinx platform usb jtag with other vendor devices

facing problem in creating ..BMM file with RAMB18X2 [2 articles]

lilaisgr8 - 2011-09-08 23:12:00
Hi, i usually do ROM merge using Data2mem, but this time my design use RAMB18x2 inside it they split it for RAMB18_Upper and RAMB18_Lower, but RAM instance remain same for both RAMB18_upper and RA...facing problem in creating ..BMM file with RAMB18X2

POST_CRC in Spartan-6 [2 articles]

Lars - 2011-09-08 10:17:00
Hi all! Anyone tried using the post-configuration scrubbing function in Spartan-6? I am a little at a loss reading the documentation, so any first-hand experience would be valuable. From the config...POST_CRC in Spartan-6

Altera Cyclone 4 deserialization, banks, pll

Serkan Oktem (Alumni) - 2011-09-08 04:59:00
Dear Gurus; I have 1 Cyclone IV GX EP4CGX150(DF27C7) This Cyclone IV is connected to 6 x Cyclone III (C40F484) All of these 6 Cyclone IIIs will send 4 bit LVDS serialized input data and a clock(...Altera Cyclone 4 deserialization, banks, pll

Virtex-6 XC6VHX380T Master SPI Configuration Problems.... [3 articles]

Jesper Kristensen - 2011-09-07 00:28:00
Hello Group. I'm currently fighting a custom-designed Virtex-6 XC6VHX380T Master SPI loading problem. Everything seems to go smoothely - Clock and Read command (0x03) is given and the PROM retur...Virtex-6 XC6VHX380T Master SPI Configuration Problems....
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