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Comp.Arch.FPGA


Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.

There are 16329 threads in our archives.

You are looking at page 13 of 1633.

The threads with the newest articles are listed first.

Please help, Xilinx FIFO problem! [56 articles]

Antti - 2010-01-28 11:33:00
I hope my plea will not be seen as usual "please help me" request. I do my (home)work, I try hard but sometimes there come up problems that seem very hard to solve, with the current problem, well if...Please help, Xilinx FIFO problem!

Achronix FPGA [14 articles]

Kastil Jan - 2010-01-28 03:47:00
Hi all, is there anybody with experience with FPGAs from company Achronix (www.achronix.com)? I found only a few documents on their web. It looks interesting to me but I was not able to find any ...Achronix FPGA

(correction)data transfer between PC and DE2 board

summer - 2010-01-27 20:29:00
HI everyone, I'm trying to send 16 byte data block from PC to DE2 board and then the DE2 board will transfer back the data to PC using bulk transfer. For the firmware part, I do modify the ReadE...(correction)data transfer between PC and DE2 board

data transfer between PC and DE2 board

summer - 2010-01-27 20:17:00
HI everyone, I'm trying to send 16 byte data block from PC to DE2 board using bulk transfer. I do modify the ReadEndpoint, WriteEndpoint and SetEndpointConfiguration to read and write 16 bytes...data transfer between PC and DE2 board

AWGN TESTING [2 articles]

hassantalal - 2010-01-27 20:09:00
HELLO .. I want to test my transmitter for AWGN .. i have coded my transmitter and receiver using VERILOG hdl .... kindly if anybody has verilog code for AWGN .. where i can change SNR values .. and c...AWGN TESTING

VHDL Manipulation and Generation Intrerface - vMAGIC 0.3.0 released

CP - 2010-01-27 07:00:00
The new vMAGIC release includes a number of new features, such as a new type handling system, simplified expression building, customizable VHDL output, and (finally) support for several things that ...VHDL Manipulation and Generation Intrerface - vMAGIC 0.3.0 released

GTKWave 3.2.0 for Windows is available [11 articles]

Muzaffer Kal - 2010-01-26 20:11:00
Hi everyone, the latest version of GTKWave (3.2.0) windows binary is available at here: http://www.dspia.com/gtkwave.html -- Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspi...GTKWave 3.2.0 for Windows is available

SystemVerilog Verification Example using Quartus and ModelSim [17 articles]

jjlindula@hotmail.com - 2010-01-25 15:39:00
Hello, I've been using the Quartus Simulator for many years and have recently started learning about the SystemVerilog Verification. I was hoping to find someone that has done this and is using Quar...SystemVerilog Verification Example using Quartus and ModelSim

simulation+configuration with Ethernet Lite MAC (xilinx)

xenix - 2010-01-25 14:44:00
Hello all, I am trying to test configure and test one design using microbl;aze and xps_ethernetlite. I am making a testbench for the modelsim but it is doesnt work. i am trying to find a tutorial...simulation+configuration with Ethernet Lite MAC (xilinx)

State Machine Initialization in Synplify Pro [9 articles]

rickman - 2010-01-25 12:33:00
I am using Synplify Pro that came with Lattice ispLever and I am getting the following warning message... Initial value is not supported on state machine TTSuperCnt It points to the line starti...State Machine Initialization in Synplify Pro
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