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Comp.Arch.FPGA


Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.

There are 16714 threads in our archives.

You are looking at page 13 of 1672.

The threads with the newest articles are listed first.

PN crashing (64 bit) [2 articles]

Roger - 2010-07-02 08:10:00
I have version 12.1 WebPack running on Vista 64. I've created a new project (the Stopwatch one in the Tutorial) and am trying to add source files. When the Add Source window appears all is OK but ...PN crashing (64 bit)

altshift_taps for Xilinx? [8 articles]

Gladys - 2010-07-01 07:05:00
Hi all, I'm developping a firmware using Xilinx FPGA spartan3, I want to use an FPGA core which has the same functionality as altshift in Altera FPGA, I was thinking about using FIFO but I need t...altshift_taps for Xilinx?

Automatic BUFG insertion on a non clock signal in ISE 12.1 [8 articles]

Amish Rughoonundon - 2010-06-30 20:33:00
Hi, I have a very simple design using a latch. I know latches should not be used but it is a necessary evil in this case for speed reason. If someone can find as fast of a way to do this with sync...Automatic BUFG insertion on a non clock signal in ISE 12.1

Binary integer to ASCII string in HDL? [4 articles]

John Speth - 2010-06-30 16:45:00
I need to do some fast ( ...Binary integer to ASCII string in HDL?

Testbench [3 articles]

maxascent - 2010-06-30 11:30:00
I am not sure if such a program exists, but I would like to be able to test a fairly large design by not having to write lots of testbenches. Idealy I would like a program were I could connect my DUT ...Testbench

Require a solution - LVDS support +RJ45 connectors [3 articles]

sharath20284 - 2010-06-30 09:42:00
Hello, I am not sure if this post is in the right place - I hope to get some help I am looking for a PCI/e based FPGA solution - The board should be able to support LVDS with 2 RJ45 i/o ports wh...Require a solution - LVDS support +RJ45 connectors

MicroBlaze - how to instantiate/connect more BRAM to the LMB [4 articles]

vivek1609 - 2010-06-30 09:22:00
Hi, I am working on the creation of MicroBlaze. I am able to generate single BRAM of 64 KB. I would like to have many BRAM (say 4) each of size 8KB connected to the LMB Bus of the MicroBlaze. Can a...MicroBlaze - how to instantiate/connect more BRAM to the LMB

ML605 Dev Board Problems [2 articles]

steveb - 2010-06-30 00:46:00
We are struggling to get the ML605 board running on our Dell PowerEdge SC430 in slot 4 (x8 slot). Out of the box the unit did not recognize the card but I could view the system PCI architecture using...ML605 Dev Board Problems

error in XPS

ravihma - 2010-06-29 14:38:00
Checking expanded design ... ERROR:NgdBuild:604 - logical block 'mult_ipif_0/mult_ipif_0/USER_LOGIC_I' with type 'user_logic' could not be resolved. A pin name misspelling can cause this, a m...error in XPS

Using Xilinx TFT controller IP for normal VGA port on Spartan 3E 1600 starter Kit [3 articles]

Manmohan - 2010-06-29 02:23:00
Hi all, I would like to incorporate into my design a VGA controller . For this purpose, I am planning to use the Xilinx XPS TFT controller IP which has the VGA signals included in it. However, ...Using Xilinx TFT controller IP for normal VGA port on Spartan 3E 1600 starter Kit
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