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Comp.Arch.FPGA


Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.

There are 16714 threads in our archives.

You are looking at page 14 of 1672.

The threads with the newest articles are listed first.

help with OVL on Actel tool [2 articles]

tullio - 2010-06-28 18:46:00
Hi, I am a verilog designer and I'd like to try OVL on an Actel design. I can't figure out how to use the OVL library. I downloaded it, but in the Actel Libero tool I can't find any way to add ...help with OVL on Actel tool

Altera Stratix4GX PCIe card as a root-port

Test01 - 2010-06-28 16:00:00
I wanted to know if anyone has used the Altera Stratix4GX PCIe card as a root port. I have used it as endpoint but have not used as a root- port. As an endpoint all I have to do is plug in the car...Altera Stratix4GX PCIe card as a root-port

Free bitmap font [10 articles]

Giorgos Tzampanakis - 2010-06-27 06:26:00
I want a simple bitmap font to use in my project. I'm looking into using a 80x25 or 80x24 format. Where can I get a font like this in an easy format to incorporate into my project? ...Free bitmap font

how to know that SRL16 was infered on xilinx? [2 articles]

onkars - 2010-06-25 16:09:00
Hello, I am implementing a core from xilinx (FFT) and wanted to know how the feedback shift registers are implemented. The xilinx core manual says that the earlier stages that need large shift re...how to know that SRL16 was infered on xilinx?

Please suggest NON Volatile FPGA Devices [3 articles]

asimlink - 2010-06-24 18:52:00
Hi Group, Could you guys please recommend me a non volatile fpga (which can hold its bit stream in, an on-chip flash). I might need to put a soft core cpu in the fpga as well. so a medium size d...Please suggest NON Volatile FPGA Devices

Help with VGA controller in Verilog [10 articles]

Giorgos Tzampanakis - 2010-06-24 18:50:00
I've been trying to code a simple VGA controller to run on my Altera DE1 board. You can see my code here: http://pastebin.com/GMfxs6Xz Note that my board has a DAC which converts the 4-bit di...Help with VGA controller in Verilog

Allocation

Jon - 2010-06-24 13:34:00
I have helped support many of the users of this group with long lead time, allocation and obsolete parts. The support usually starts off with FPGA 's, but has led into other many other semiconductor...Allocation

SDRAM capacity using Petalinux [2 articles]

rduar002 - 2010-06-23 17:48:00
Hi, I successfully ported Petalinux on the XUPV5-LX110T FPGA board using 8 KB of Data/Instruction Cache. My SDRAM is 256 MB (MT4HTF3264HY-667F1). However when I create a file (vi myFile) at the /var/...SDRAM capacity using Petalinux

Xilinx Timing Constraings [10 articles]

Rob Gaddi - 2010-06-23 14:14:00
I'm no luck figuring out how to implement the timing constraints for something that, to my mind, ought to be pretty simple. I'm connected to an external synchronous logic chip. For now let's cal...Xilinx Timing Constraings

Spartan-3E starter kit USB schematics ? (again) [3 articles]

EvSpace - 2010-06-23 12:17:00
On the Xilinx Spartan-3E Starter kit board there is an USB interface to program the FPGA chip via JTAG. However this part of the schematics is missing from the documentation: http://www.xilinx.com/...Spartan-3E starter kit USB schematics ? (again)
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