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Comp.Arch.FPGA
Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.
There are 17402 threads in our archives.
You are looking at page 14 of 1741.
The threads with the newest articles are listed first.
Xilinx ISE Design - XPS won't start
z master - 2011-09-06 06:24:00
Hello everyone,
Recently I installed Xilinx ISE Design Suit 13.1 for studying. I got
the licence right and everything, but unfortunately I faced a few
strange problems... First of all, I can't ru...
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xhtml champs - 2011-09-06 01:35:00
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xhtml css services. Includes web designing services, logos, b...Webhosting, Domain Name, Data Center Cyprus, Hosting Services
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ht...What is the advantage of source-syncronization (in SDRAMs)? [20 articles]
valtih1978 - 2011-09-02 13:58:00
The data arrives with some unknown phase shift relatively to system
(synchronized to SDRAM) clock. DQ can be captured more reliably if we
route the data clock, DQS, along the data. They suggest th...5V FCT TO Cyclone II [8 articles]
majsta - 2011-08-30 17:33:00
Hi there, i just fount this page and i hope that you can help me. Here is
what i need to do. I want to interface MC68000 to cyclone II. As you
allready know MC68000 is 5V system and i need to convert ...A free lunch [6 articles]
Jan Decaluwe - 2011-08-30 05:35:00
The Python community is about to offer us a free lunch.
A new compliant interpreter, pypy, is already 4.3x faster
than cPython, and getting faster everyday. It shows
that there is not conceptual re...Very cheap Spartan3 board that can be configured by simple USB [19 articles]
Giuseppe Marullo - 2011-08-29 21:00:00
Hi,
I would like to know which is the smallest (read cheapest) board with a
Spartan3 that can be programmed directly by a usb cable.
I just need a couple to test a design that must be operated r...Boundary scan [4 articles]
salimbaba - 2011-08-29 15:38:00
Hi,
i wanted to know whether there exists any software that can be used to know
whether all the balls of my bga grid are properly fixed in place or not.
Actually i am using spartan 3 xc3s4000 and ma...DSP power consumption in Virtex devices...
Xesium - 2011-08-29 13:33:00
Hi All,
I remember a while ago I read an article on Xilinx website regarding
low power modes of DSP blocks and Block RAMs on newer virtex devices
(V6 and V7 I guess). I know of suspend mode in Spar...cheating Arria FPGA i/o count [20 articles]
John Larkin - 2011-08-28 18:18:00
Hi,
I'm designing a pretty horrible board (33 page schematic!) that will
use an Altera Arria II GX in the 572BGA package. There are 240 pure
I/O pins in this package, and 12 dedicated clock pins....