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Comp.Arch.FPGA
Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.
There are 16332 threads in our archives.
You are looking at page 15 of 1634.
The threads with the newest articles are listed first.
Easy PC software tool - Bad experience [11 articles]
Roger - 2010-01-21 21:22:00
Due to a bug in the Easy PC software tool from Numberone Systems, I've just
had a very time consuming and costly incident. Despite their faulty software
costing me a lot of money, the company have...
Icarus Verilog opinions
Giorgos Tzampanakis - 2010-01-21 19:13:00
I've been trying out the Icarus Verilog compiler/simulator. It
looks nice so far. Any views on it?
Also, it claims that it can generate code to load onto real
FPGA's. Can it really do that? Has...user ip in edk
gentel - 2010-01-21 09:02:00
hi,all
i have created an user ip connecting opb bus based microblaze.when i
watch the data from many ports in chipscope ,there is a strange Phenomenon.
i can obtain only one right data from t...Simulation of VHDL code for a vending machine [26 articles]
glallenjr - 2010-01-21 08:54:00
Currently I am studying the "Circuit Design with VHDL" by Volnei A.
Pedroni. On page 207 the run a simulation but do not provide the test
bench. I would like to run the same simulation but I am not fa...A construction of FPGA based design by a beginner [3 articles]
Alex - 2010-01-20 11:37:00
Hello All,
I am a beginner and want to get an idea how to construct actual FPGA-
based design (a PCB) after this was developed and tested using
development board (I use Xilinx Microblaze 1600E de...USB transfer for DE2 board
summer - 2010-01-20 07:28:00
HI everyone,
I'm trying to send 16 byte data block through DE2 board.
Does anyone have experience on this?
I do modify the ReadEndpoint, WriteEndpoint and SetEndpointConfiguration
coding. But I s...compiler output to fpga. [6 articles]
akshayvreddy - 2010-01-20 04:08:00
Hello,
I am implementing a processor design on the virtex 2 chip. The Design was
done using verilog with Xilinx 10.1 and modelsim. I have a compiler of the
design.
My question is:is there a way ...IEEE fixed_pkg not recognized in ISE 11.1 [4 articles]
axr0284 - 2010-01-20 03:35:00
Hi,
I was wondering why this declaration in my code:
use IEEE.fixed_pkg.all;
spits out this error when I try to synthesize in ISE 11.1
Library unit fixed_pkg is not available in library IEEE.
...Post Route Simulation for IP CORES
Rishvanth - 2010-01-19 14:08:00
Hi all,
I created a project which contains some xilinx IP CORES. I have
successfully tested the behavioral simulation but I'm unable to get the
post route simulation. Is there a way to get a post r...XST is driving me mad. [7 articles]
ghelbig - 2010-01-19 13:45:00
I've been trying to make a _simple_ counter work, and it just doesn't.
Can I get another set of eyes to look at this? It's probably
something dumb/simple, but I just can't see it.
The code:
...