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Comp.Arch.FPGA


Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.

There are 16714 threads in our archives.

You are looking at page 15 of 1672.

The threads with the newest articles are listed first.

Question about Altera NIOS II, Eclipse, Quartus subscription try version 9.1

fl - 2010-06-22 21:36:00
Hi, I am new to Altera Eclipse for quartus subscription 9.1 version. I want to learn NIOS programming. I go through the simpliest version on 'Getting Started' part in "Nios II Software Developer's ...Question about Altera NIOS II, Eclipse, Quartus subscription try version 9.1

Xilinx DCM Block Stability Issues [10 articles]

Randy Yates - 2010-06-22 21:24:00
Hi, We're using one of the global DCM blocks in a Xilinx Spartan 3E to regenerate/deskew an important clock in our application. The clock has an input frequency of 31.5 MHz and we're using the 27...Xilinx DCM Block Stability Issues

Polmaddie Low Cost CPLD/FPGA Boards Update

John Adair - 2010-06-22 15:18:00
There are now new user manuals and schematics for Polmaddie1, Polmaddie2 and Polmaddie3 boards. Polmaddie4 and Polmaddie5 to follow shortly. Jump page to all of these boards http://www.enterpoint.c...Polmaddie Low Cost CPLD/FPGA Boards Update

Asynchronous FIFO in Spartan6 [4 articles]

Sebastien Bourdeauducq - 2010-06-22 14:17:00
Hi, I am trying to use this FIFO design in a Spartan6: http://www.asic-world.com/examples/verilog/asyn_fifo.html Doing so makes Xst emit a shrill warning (Xst:3002) because a latch construct d...Asynchronous FIFO in Spartan6

ASIC solution to UVC and FPGA interconnectivity [2 articles]

allsey87 - 2010-06-22 09:27:00
Hey all, Does anyone know of an ASIC chip from NXP, Motorola etc which will interface a webcam using the UVC (USB video class) protocol. Ideally the chip would simple as possible and drop out 8/1...ASIC solution to UVC and FPGA interconnectivity

how fast is ... fast. [10 articles]

LC - 2010-06-22 06:46:00
Hi, In a design I'm working on I have a machine that produces 128 bit of data. This data is destined to a 16 bit DAC running 8x faster. Knowing that I can produce the 128bit up to a 120MHz rat...how fast is ... fast.

RAM issues with Plasma CPU on Nexys 2

Jon - 2010-06-21 19:09:00
Hi guys, at first some background information: I'm doing a study project for some weeks now which is about "VHDL development environment for FPGA". The first goal was to set up ISE WebPack under ...RAM issues with Plasma CPU on Nexys 2

Anyone interested in customizable EDA software for FPGA? [3 articles]

Yujie Wen - 2010-06-20 03:46:00
Hello. I am working at an SoC startup developing EDA software for FPGA-like structures. Currently we have a half-finished software covering from technology mapping to placement and routing for FP...Anyone interested in customizable EDA software for FPGA?

GTKWave 3.2.0 for Windows is available [12 articles]

Muzaffer Kal - 2010-06-20 02:40:00
Hi everyone, the latest version of GTKWave (3.2.0) windows binary is available at here: http://www.dspia.com/gtkwave.html -- Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspi...GTKWave 3.2.0 for Windows is available

Difficulty with Xilinx FPGA configuration using Platform Flash PROM [5 articles]

Vic Orloff - 2010-06-19 16:57:00
Hello, I am a beginner and have tried to learn how to configure my FPGA (XC3S1600E) in Master Serial Mode using configuration of a design stored in Platform Flash PROM (XCF04S) . I use Xilinx IS...Difficulty with Xilinx FPGA configuration using Platform Flash PROM
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