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Comp.Arch.FPGA
Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.
We found 1217 threads matching "xst"
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Re: Dumb VHDL Question -- Type Conversion
Andy Peters - 2010-07-23 19:29:00
On Jul 19, 4:23=A0pm, Andy wrote:
> I recommend using integer for arithmetic if your data paths are less
> than 32 bits. Mod has been well supported for quite a while (it was
> then if you used decent FPGA tools), and is very handy for making sure
> you don't have overflows (which do no...
Looking for recent Altera Quartus Verilog synthesis experience
John Providenza - 2003-10-01 13:22:00
I'm looking at doing a design with Apex-II parts and will
probably need to use the Verilog synthesizer that comes with
Quartus. My last experience (multiple years ago) was very
unpleasant - lots of synthesis bugs.
Has this gotten better?
My experience with XST synthesis recently has bee...Re: Doubts on Xilinx FPGA
John_H - 2005-07-16 19:51:00
"Dear john" ...my oh my.
Counters are registers.
1) You can always use the INIT=S and INIT=R attributes on the individual
bits of the counter word in your ucf file.
2) If you're using XST, you might be able to use the initial definition
reg [7:0] counter = 7'ha5; // to initialize to hex v...connecting block ram to datapath using bidirectional lines
Xizen - 2005-08-27 20:16:00
Hi ,I've been working on this for three days and I got lost in the sea
of XST warnings and errors .... I'm really lost.. In short ,what I
want is to design a combinational module that will interface between
the datapath of a cpu with blockram's bidirectional datalines..the
module should include an i...Re: Which HDL?
Joseph H Allen - 2005-03-16 10:19:00
When will the FPGA vendors support system verilog? System Verilog adds
structures to Verilog 2001, so you can say: bus.data, bus.addr, etc.
When will VCS support Verilog 2001? It lacks the ability to make
parameterized modules if you use the new "ANSI" style declaration syntax:
module foo ...XPS: Create/Import File structure
2005-05-18 16:28:00
I am trying to use a 3rd party IP core I2S_OPB as a peripheral in my
microblaze hw design. When using the Create/Import Peripheral wizard I
an getting error that it cannot find my library.
I think I am tripping over a file structure issue. Where should I put
my I2S_OPB_package file in order fo...Some doubts in the FPGA design flow in the ISE
subint - 2007-06-01 06:39:00
Hi,
I am not been able to understand the details of the each stage in the
design flow.
Actually what are the things happening in the mapping stage? During
low-level optimization itself, XST infers specific components (is this
time itself it's checking the available components in the FPGA).
If...area constrains in UCF (or PACE)
Yttrium - 2004-02-28 08:19:00
hey, for now i just use
AREA_GROUP "AreaGroupName" RANGE = SLICE_X0Y79:SLICE_X27Y54 ;
INST "/" AREA_GROUP = " AreaGroupName " ;
as area constraint but i can't really find how you can place your individual
components?
let's say you have a root component A which is composed by components B ...synthesis error
Thorsten Kiefer - 2008-06-26 12:24:00
Hi,
synthesizing the following code yields an error.
CODE :
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:22:54 06/23/2008
-- Design Name:
-- Module Name: main - Behavioral
-- Project Name: ...Re: ports of multidimentional arrays in verilog.
Jeff Brower - 2006-05-03 22:18:00
CMOS-
> using verilog how to write a module which has an inpput port for an
> array of 8 bit signals and how to write a test bench for it.
Wait until you try to initialize your arrays. Try this search in
Google Groups:
initializing array of registers in XST group:comp.arch.fpga
It...Re: Using memory blocks generated by CoreGen
Jan Bruns - 2009-01-18 13:17:00
"Ehsan":
> I've written a VHDL entity in which I'm instantiating a distributed
> memory block generated by Xilinx CoreGen. Now, I want to use this
> entity a number of times in a bigger design. In each instantiation, I
> need to initialize the memory with different contents (.coe file).
>...BRAM synthesis question
Paul Boven - 2008-03-11 09:55:00
Hi everyone,
While trying to build a simple VGA driver, I'm running into trouble
getting my video-ram (actually, sample ram) to be synthesized as a dual
port block-ram - it keeps wanting to use up 25% of my LUTs. I've tried
to describe the BRAM as instructed in the xst.pdf documentation, but a...Translate fails in ISE 8.1
motty - 2006-09-25 13:38:00
If I try to run the 'Implement Design' process in my project, the ISE
errors out immediately. There is NO message in the console...no
indication of what may have failed. The synthesis reports OK. The
only warnings in that are for ignored delay values and one unconnected
port at the top level....Re: Bresenham Algorithms
Ben Twijnstra - 2005-05-24 18:41:00
Hi Jake,
> I've got lots of VHDL (and Verilog) only for Xilinx. Instantiate a
> Xilinx primitive and it suddenly becomes very difficult to synthesize
> using Altera tools (unmodified, that is).
What kind of stuff do you need to instantiate then? I can imagine the DCMs
and the MGTs becau...error during ise simulation
2009-01-11 07:45:00
hi all
i had designed a module for controlling a steeper motor using vhdl in
modelsim where it worked perfectly fine. but while trying to
synthesize the same code in ise the following error message was
displayed.
FATAL_ERROR:Xst:Portability/export/Port_Main.h:127:1.17 - This
application has di...Re: Time for a new "Largest FPGA with free tool support"?
2006-06-15 13:54:00
mk wrote:
> You're right, I
> don't think anyone is asking for LX200 to be supported by free tools
> but something larger than S3E 1600. How about it?
Actually, you got that wrong, as people have, including myself.
Admittedly all that I've asked for is that place, route, and bitgen be
f...[xst]:clk information question
Tim Verstraete - 2005-10-31 08:13:00
This is a multi-part message in MIME format.
------=_NextPart_000_0010_01C5DE25.3647F990
Content-Type: text/plain;
charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
Hey,
i made a design for a LVDS input (with some tweaks) and the design is =
working but i found this...Synthesis changes after ISE upgrade
Yaseen Zaidi - 2006-07-03 07:15:00
I just upgraded ISE 6.3.03 to 8.1 and already I am experiencing varying
synthesis results. For one thing I do not infer FSM any more and the
next states are bunch of latches. There is unexpected ROM inference
though. This design is synchronous and works fine in ver 6 both at
behavioral and gate ...Using BUFG with internally generated clocks
Di Pascale - 2005-03-08 17:22:00
I'm trying to use a Xilinx XC2VP20 (Virtex II Pro family) to prototype
an ASIC device but I'm experiencing a lot of trouble cause i'm new to FPGA.
The problem is that my project has various asyncronous clocks generated
internally by means of dividers and NCOs. I would like to route these
cloc...Re: ISE 8.1 Comment Bug, Very hideous
Antti - 2006-05-01 12:11:00
some long time ago writing your company name in non-ascii chars like
a-umlaut a" in the schematic template header of the Xilinx ECS rendered
the schematic to invalid, so you lost your work (ok it was possible to
use binary editor to fix the char)
- the comment type of error in Xilinx ISE/XST m...Design Implementation in Xilinx XST
Jeremy Wood - 2005-11-23 09:19:00
Greetings everyone,
I've recently started working on FPGA designs and was wondering if
there is a way to get timing reports and synthesis results from the
Xilinx software that don't include I/O pin mapping. I'm trying to
constrain several blocks for testing purposes, but these modules will
al...Re: beginner synthesize question - my debounce process won't synthesize.
Brian Drummond - 2009-01-10 10:40:00
On Thu, 8 Jan 2009 12:31:26 -0800 (PST), jleslie48
wrote:
> On Jan 8, 2:52 pm, Brian Drummond
> wrote:
>
> >
> > > In other words, if I re-write my repeat 10 loop as such:
> >
> > > looper10_proc: process (CLK,RESET)
> > > variable icount : integer := 0;
> > > begin
> > > ...Xilinx ISE 11.1 crash - Visual Studio error
Daku - 2010-02-09 00:04:00
Could some Xilinx ISE guru provide some hints for my problem ? I am
trying to synthesize a simple 4K RAM block with Xilinx ISE. About half-
way through execution, I get an error message, inside a Visual Studio
dialog box, stating that xst.exe ( the Xilinx synthesis executable)
has encountered a ...Signal encoding for a user-defined type
shantesh - 2009-05-27 08:28:00
Hello,
I'm running a back-annotated simulation for which I need to know the
encoding scheme for my signal.
XST reports, "Found 4-bit register for signal
where to_bus.request is of type
(read_36,read_72,read_line,read_device,write_36,write_72,write_line,
write_device,nothing,return_...Does synplify 8.8 can support xilinx virtex5?
2007-07-05 04:56:00
I use synplify 8.8 to synthesis my design. And my design contain
xilinx ip core (generated by core generator). My design can be
synthesis with XST. But when I use synplify 8.8, synthesis cannot be
done successfully. It seems that synplify does recognise xilinx ip
core.Do i need to set some optio...Re: Xilinx Sum in VHDL
Brad Smallridge - 2005-01-20 18:24:00
> Umm, you're *not* 'doing 8 bit work'?!?
Hello Mark,
OK, it seems to me that the best solution is
one eight bit adder with a carry, going into
a nine bit adder (maybe not if I don't care about
the lower bits) with a carry, giving me a 10 bit sum.
My question is (was), does this VHDL ...Re: State Machines....
Goran Bilski - 2003-11-20 13:45:00
Hi,
The latest version of XST in ISE 6.1 have an option to synthesize a
state machine using BRAM as a resource instead of LUTs.
It's called FSM_STYLE
Göran
Mike Treseler wrote:
> Jim Granville wrote:
>
> > It is a good idea, but the SW tool side could need work to help it take
>...Re: EDIF generation from Verilog in ISE 6.2i
2004-09-10 05:00:00
"apai" writes:
> I wanna generate EDIF netlist from Verilog code. I am using Xilinx
> ISE6.2i software, and cannot find any trace of EDIF netlist
> generated.
I don't think XST can generate EDIF anymore. If you want EDIF you need
to use a third party synthesis tool like DC-FPGA.
...Re: Synthesis in VHDL vs. Verilog
Uwe Bonnes - 2004-01-07 14:40:00
Chris Carlen wrote:
...
: Is there good modeling style info in Xilinx tools so that one can learn
: how to make synthesizable models for Xilinx tools reliably?
Look on the XILINX site fir xst.pdf amd lib.pdf
...
Bye
--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt...Re: IP-Core CAN-Controller
Antti Lukats - 2003-09-08 09:42:00
Daniel Köthe wrote in message news: ...
> Hello,
> i looking for a SJA1000 or compatible IP-Core for an Spartan-II.
> There are other's Sources as Xilinx-Core program or Opencores?
there are lots of sources, but ASFAIK the only free CAN-IP is at
opencores, and unfortunatly current vers...Re: Graphic LCD
KCL - 2005-02-20 11:09:00
I'm also interseted in it
I'm writing an VGA display with incorporated ROM font , for test I just
implemented part of font but in the future I will have to implemente all the
font so knowing how to generate a file for the rom should be interesting.(I
have already made a ROM for an altera co...Re: Xilinx ISE 8.1i Trouble
Ben Jones - 2006-06-20 12:11:00
"Alex" wrote in message
news:1150811188.026823.5240@r2g2000cwb.googlegroups.com...
> The error that I'm getting is:
> NCD was not produced. All logic was removed from design. This
> is usually due to having no input or output PAD connections in the
> design and
> no nets or ...Re: fpga express 3.6
Jonathan Bromley - 2011-03-27 12:39:00
On Sun, 27 Mar 2011 08:42:30 -0700 (PDT), electrocoder
wrote:
> i want "fpga express 3.6" setup program. i have "ftp://ftp.xilinx.com/
> pub/swhelp/M3.1i_updates/fpgaexp35.exe" update files. i want setup
> program. thanks.
FPGA Express has been very dead and very unsupported for
a very ...Xilinx hypertransport lite reference design.
Aniket - 2004-05-21 02:15:00
Hi all,
Has anybody used the hypertransport lite reference design provided by
Xilinx.
I cant seem to get it to work.
I unzipped the design and changed the synthesis tool to xst.
The VHDl design dosent synthesize and the verilog version synthesizes
but when the simulator is run it gives a...Re: Xilinx ISE 8.1 Makefile
John Retta - 2006-05-09 15:39:00
Here is sample .bat file that I typically use for command
line synthesis ... that bypasses gui entirely. There are lots
of advantages to command line flow ... Entire synthesis
flow is documented ( and can be archived) in text document.
Portability of synthesis flow among workstations/PCs is
en...Spartan-3 3S50 in Web ISE 5.2i = no block RAM, no multiplier?
Kirill 'Big K' Katsnelson - 2003-09-09 23:04:00
I downloaded Xilinx free Web ISE 5.2i, and toying with different design to get
the feeling of this Spartan-3 thingy. The only Spartan-3 device supposed to be
supported by the free verison is 3S50. I am saying "supposed", because I cannot
make it instantiate neither multipliers nor block RAMs. ...xst and fpga express
uckingcu - 2006-03-28 14:37:00
Hi all,
i am working in a network security company..i got a question..i
am using a very big design targeted for xilinx virtex2 xc2v3000 device..i
found a interesting problem recently...i used my design with
xst7.1,everything works fine in functional simulation but after i download
onto f...Re: Xilinx Virtex-II Newbie
Andrew Ganger - 2007-11-14 11:48:00
> 1) I had some kind for simple RAM for simulation. How can I implement
> this RAM correctly so that it be sythesizable and will correctly run on
> the FPGA?
>
> 2) When I start the processor, I should have my instructions loaded into
> the Instruction RAM? How can I do this, really n...Xilinx/Linux: sch2vhdl not working very hard
Paul Boven - 2005-10-02 12:14:00
Hi everyone,
Now that I've got the Xilinx Web-tools running reasonably well under
Linux, I'm noticing that sch2vhld, which converts a schema-drawing into
vhdl, is spending almost all of its time waiting. It's not using the
CPU, disk or network at all. This happens both when called from the ...Re: reconfigurable, modular design and clock signals - Question
L. Schreiber - 2007-12-10 05:33:00
austin schrieb:
> L. Schreiber,
>
> The module flow was removed from this app note (no longer supported).
>
> PlanAhead is available to universities through the XUP (Xilinx
> University Program). Ask your professor to request a copy and a license.
>
> Austin
Now it's working ...