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Comp.Arch.FPGA
Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.
There are 17402 threads in our archives.
You are looking at page 16 of 1741.
The threads with the newest articles are listed first.
[actel] resource usage by entity [3 articles]
kclo4 - 2011-08-23 08:10:00
Hi ,
I am currently designing a FPGA Actel Proasci3 and I would like to
know the ressource usage (ram/flipflop...) for each of module of the
project , in Altera and Xilinx they report this inform...![[actel] resource usage by entity](http://www.fpgarelated.com/new/images/
icon_more.jpg){kind=small}
Testbench in verilog ps and human interactions don't mix [4 articles]
Giuseppe Marullo - 2011-08-22 09:49:00
Hi all,
I am testing a fairly slow design ( a IAMBIC keyer) and while I am
dealing with slow signals (up to 120 WPM, about 10ms minimum resolution)
I would like to perform very precise measuremen...Altera Flex10K support ? [6 articles]
Nicolas Matringe - 2011-08-22 02:29:00
Hi
I have found old parts lying around in the lab and I could put them to
good use. Alas, they are not supported by Quartus any more. Do you know
which version of the tool I should get (and where...VHDL Basic Question [13 articles]
maxascent - 2011-08-21 15:40:00
I am new to VHDL and need some advice on connecting a vector array on an
entity using a port map.I have an array of std_logic_vectors(63 downto 0)
as a port. There are 3 of these in the array. How do ...Synthesizable heap-sorter for FPGA - BSD licensed sources [5 articles]
wzab - 2011-08-19 14:09:00
Hi,
I have prepared a heap-sorter implementation for FPGA. The sources are
licensed under the BSD license and
are available at alt.sources group.
Due to the fact, that I'm on my holidays, I was ...image storing into BRAM [10 articles]
balajigec - 2011-08-19 01:52:00
dear all,
i want to store image from PC to BRAM of an FPGA.i have image 192x96 size.
1) which type of interfacing should i use to transfer image into BRAM from
PC
2) how to write a program for it? ...DVI-decoder clock question [4 articles]
Mawa_fugo - 2011-08-17 16:02:00
Let say I have two DVI streams - generated by two encoders, those have
different video contents but same pixel clock
The two tmds streams travel thru cables then - are decoded by two
decoders - t...Help needed to emulate a microcontroller. [14 articles]
foxclab01 - 2011-08-17 00:58:00
Hello to all.
I am very new in FPGAs but I have good experience in microcontrollers. I
need a very high frequency microcontroller for a project. I tried the
PIC32MX575F512L from microchip, which ca...Need some engineers [3 articles]
Jody Singleton - 2011-08-16 10:22:00
Electrical Engineer/Embedded Firmware
Established engineering firm has immediate need for Electrical
Engineers. Projects involve embedded control applications using
Xilinx and MicroChip products a...VHDL horror in Xcell 76 [8 articles]
RCIngham - 2011-08-16 00:12:00
There is an utterly horrible VHDL howler on page of 45 of the latest Xcell
Journal. Two example codes for a register with reset are given:
signal Q: std_logic:=‘1’;
...
async: process (CLK,RS...