Sign in
Search Comp.Arch.FPGA
fpga by Keywords
Altera | ASIC | CPLD | Cyclone | DCM | DDR | DSP | Ethernet | ISE | JTAG | Linux | LVDS | Microblaze | ML310 | Modelsim | NIOS | OPB | PCI | Quartus | RocketIO | SDRAM | Spartan | Spartan3 | SRAM | Stratix | Verilog | VHDL | Virtex | Virtex-4 | Virtex-II | Xilinx | XST
Ads
See Also
Comp.Arch.FPGA
Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.
There are 16714 threads in our archives.
You are looking at page 16 of 1672.
The threads with the newest articles are listed first.
Expand TEMAC fifo? [4 articles]
Griffin - 2010-06-18 20:30:00
Hello,
I'm working on an embedded project (EDK 11.2) and am using the TEMAC
IP core (xps_ll_temac) and the TEMAC fifo (xps_ll_fifo).
From what I can tell, the size of the Tx fifo is only 2Kb; t...
Anyone else need bigger parts in small (low pin count) packages [30 articles]
rickman - 2010-06-18 18:26:00
I am looking at reducing the cost of a board while improving the
performance and one way is to add a processor to offload the low
bandwidth portions of an FPGA design and then reduce the capacity of...Trouble with Altium Openbus document based UART example using TSK3000A [2 articles]
asimlink - 2010-06-17 09:11:00
Dear Friends,
i am using Altium Designer for fpga and embedded project on digilent
spartan3E-500 board.
I have created an FPGA project in Altium using open bus document containing
three device: ...How to detect a sync and start of a frame in an optimal way [9 articles]
Vips - 2010-06-17 07:21:00
Hi All
I am designing a module and I am having some issues .. Let me explain
what I am doing.
I am getting data as 64 bytes in each clock cycle . In these 64 bytes
I look for sync bits which...Decoupling for Altera Cyclone II 2C8 [5 articles]
Philip Pemberton - 2010-06-16 11:49:00
Hi guys,
I'm designing a PCB for a project of mine (a floppy disc data analyser --
see ). This will be my first project with an
FPGA, or at least the first one that's made it as far as actual P...Prog4 - Altera Programming Cable and a development board in one. [2 articles]
John Adair - 2010-06-15 15:09:00
In prep for the release of more Altera development board additions to
our range we have a new programming cable Prog4. We will be selling
this 2 ways. The first is as a programming cable and that wi...Does Xilinx Spartan 6 support NAND flash? [2 articles]
Gladys - 2010-06-15 10:37:00
According to the datasheet, The Spartan 6 family has
Broad third-party SPI (up to x4) and NOR flash support
Feature rich Xilinx Platform Flash with JTAG
I don't quite understans if it supports ...Simulation error [2 articles]
flipoo - 2010-06-15 08:05:00
Hi guys,
When i try to simulate a simple EXOR i get the following error:
# ** Warning: A ModelSim starter license was detected and will be used,
even though you have installed ModelSim XE. You s...DLC9G problem
sambad20 - 2010-06-15 07:48:00
Hi all dear
I have a DLC9G programmer for programming all FPGAs It was working good but
from some days before I don't know why but after connecting programmer to
board the LED is getting green but wh...VIRTEX5 (XUPV5-LX110T) Ethernet
budakbijak - 2010-06-15 07:47:00
Hi,
Im working on communication for the Virtex 5 using Ethernet. As a good
start, do you have any ideas/examples program which use Virtex5? I have
tried browsing on the internet, but there are not m...