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Comp.Arch.FPGA
Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.
There are 16714 threads in our archives.
You are looking at page 17 of 1672.
The threads with the newest articles are listed first.
Altera Quartus - how to create small roms & rams for Cyclone 3 [10 articles]
newzhnd - 2010-06-14 19:33:00
Help !!! The megawizard in Quartus 2 does not seem to support generating
small roms & rams using the LUT
tables, only using the M9K memory blocks. Any way to generate small roms &
rams using t...
Trouble with Altium Openbus document based UART example using TSK3000A
asimlink - 2010-06-14 13:54:00
Dear Friends,
i am using Altium Designer for fpga and embedded project on digilent
spartan3E-500 board.
I have created an FPGA project in Altium using open bus document
containing three device:
...Power Management for PCIe
Usama - 2010-06-14 03:04:00
hi
I am implementing BMD design as explained in xapp1052(v2.5). Have
implemented the design on Avnet V5LXT/SXT PCIe Development Board using
the PCIe. Have generated the Endpoint Block plus for PC...Is it possible to get consistent implementation results? [11 articles]
BrandonD - 2010-06-12 04:44:00
Hi,
I'm working with Xilinx ISE 10.1 and I am having troubles with timing
constraints.
I've successfully implemented my design with a 20 ns cycle time and found
that I needed to change something...how to interface a ddr2 memory controller to a processor [5 articles]
rana - 2010-06-11 11:49:00
hi all,
i have a ddr2 controller that works on 4 burst mode. ddr2 dq width is
16. i must provide 2, 32 bit data to the controller before writing it
to memory. As well as when reading from a memor...Alternative to Chipscope [5 articles]
apple - 2010-06-11 07:52:00
I would like to have capabilities of Chipscope for Xilinx FPGA's
are there any free alternatives to it?
a.t
...Design passes synthesis and routing but fails on FPGA [11 articles]
BrandonD - 2010-06-10 06:47:00
Hi,
I'm somewhat familiar with synthesis and Verilog but I am quite new to
running the designs on FPGAs. I have a complex design of a processor that I
am trying to get running on a Virtex 5 FPGA in...How to Disable IP Core after Evaluation Period [5 articles]
Sudhir Singh - 2010-06-09 16:18:00
Hi Guys,
I am just wondering if there are any standard ways of disabling an ip
core after an evaluation period of say 30 days. I am trying to provide
a potential customer a ip core but don't wan...Calling different modules of a project from another main file [2 articles]
sandeep - 2010-06-07 13:06:00
Hello Friends
Our group has finished a project which has
different modules in it, executing different tasks. We need to call
this different modules of the project f...Burn to an internal prom Spartan-3an [2 articles]
izaak - 2010-06-07 09:49:00
I use an internal memory Spartan 3an
When I try to burn only the FPGA I can!
Even when I try to burn the FPGA and the prom
I get in the middle of the recording process failed!
And the reason he fa...