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Comp.Arch.FPGA


Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.

There are 16329 threads in our archives.

You are looking at page 17 of 1633.

The threads with the newest articles are listed first.

How to gracefully terminate the PCIe read request [4 articles]

Test01 - 2010-01-13 02:20:00
I am using Viertex5 hardip in pcie gen1 x4 configuration. The hard IP has PCI bar register configured for 512K memory space. The Root complex is sending out the memory read request to the V5 end p...How to gracefully terminate the PCIe read request

Xilinx ISE 10.1.03 [3 articles]

Philip - 2010-01-12 13:45:00
Hi all, I was just about to download the new Xilinx ISE 11.1 evaluation package. However, I was told that the new Xilinx design suite does not support Xilinx Virtex II Pro devices anymore. Does...Xilinx ISE 10.1.03

.sopc example for PCI Express Development Kit, Stratix II GX Edition

Tim Climber - 2010-01-12 12:10:00
Hi. I'm looking for any .sopc-file example for this board. For example, how correctly connect DRAM, SRAM, "Spansion" flash and ethernet? Altera doesn't offer any examples officially. At leas....sopc example for PCI Express Development Kit, Stratix II GX Edition

XC2V2000-5FF896C or XC2V2000-6FF896C Virtex II [2 articles]

jon - 2010-01-12 10:41:00
I need help on 200 pieces of a Virtex XC2V2000-5FF896C or XC2V2000-6FF896C . I can get these from Avent, but the pricing is way above what I can pay. I don't get the special pricing. If you have any...XC2V2000-5FF896C or XC2V2000-6FF896C Virtex II

E1 clock problem... [2 articles]

morppheu - 2010-01-12 10:37:00
Hey guys... I need a little help with my E1 interface. I have an internal clock and the E1 clock. When E1 chip (MT9076B) is present I use the E1 clock + E1 F0 signals, else I use the internal cloc...E1 clock problem...

Timing errors in Post route simulation in modelsim

gentel - 2010-01-12 07:37:00
Hi, when i do post route simulation i get a bunch of error similar to the following ** Error: F:/ise/verilog/mti_se/simprims_ver/simprims_ver_source.v(109890): $setup( negedge SRST &&& (srst_clk_en...Timing errors in Post route simulation in modelsim

Old School Hurts [5 articles]

Rick - 2010-01-11 20:27:00
More venting then seeking help. I got my Diligent Sparta board and I have to say it appears to be a great value. Parts alone are worth the price. The down side is the Xilinx software DVD took u...Old School Hurts

Programming Failed

salquraish - 2010-01-11 06:21:00
I am using JTAG parallel cable to program FPGA, while programming the FPGA code into the internal flash power was disconnected and finally "PROGRAM FAILED" message was observed. I had tried to progra...Programming Failed

new PC specs for Xilinx tools [15 articles]

Tom Kotwal - 2010-01-10 16:06:00
Hi All, I'm speccing out a new windows PC that I'll use with Xilinx tools, probably Webpack and Modelsim, and I'm looking for some advice to make sure the tools will run fast. I know memory is im...new PC specs for Xilinx tools

Difference among Virtex Families, FPGA Books [11 articles]

rk - 2010-01-08 10:23:00
Hi Folks I have recently become very interested in FPGA and DSP. Could somebody suggest to me a newbee started book and also a related experimental board. I would also like to know the dif...Difference among Virtex Families, FPGA Books
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