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Comp.Arch.FPGA
Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.
There are 17402 threads in our archives.
You are looking at page 18 of 1741.
The threads with the newest articles are listed first.
Regarding process time calculation [17 articles]
varun_agr - 2011-08-05 12:41:00
Sir
I want to know that how we can calculate time taken by a process or in
Xilinx ISE anywhwhere we can see it as we are using concurrent programming
and want to know time taken by each process in be...
die's in different packages [7 articles]
Sharan - 2011-08-05 00:28:00
can someone tell me if there is any differences in the die for the
following 2 devices in virtex-7
XC7VX415TFFG1158 and XC7VX415TFFG1927
Both these devices are listed as having same logic resou...FPGA security, Actel down, now Xilinx too? [5 articles]
Antti - 2011-08-04 16:01:00
Hi
its maybe not so commonly known that there have been products using Actel s=
ecure FPGA's have been cloned already many years ago (readback done by dark=
engineers at Actel), few month ago a ...XST 13.1 explodes with generic of enum type with only one member [14 articles]
Jonathan Bromley - 2011-08-03 14:54:00
It was all going so well until I asked XST to compile a
VHDL entity with a generic of this type:
type video_modes_e is (vesa_1024x768_65Hz);
I guess I'll have more modes later, but just now I
...Pipeline stages of the Multiplier core (ISE Coregen) [2 articles]
spman - 2011-08-01 11:14:00
Hello friends
I can't understand how the Pipeline stages affect the multiplier core?
I tested 1 stage and 4 stages. The result is given with 1 clock for 1
stage, and 4 clocks for 4 stages.
When i...Post-map simulation: timing violation and delays [7 articles]
sdaau - 2011-07-28 12:36:00
Hi all,
I am trying to implement a custom counter (with clock and enable inputs);
synthesis and behavioral & post-translate simulation pass just fine (using
ISE WebPack 13.2). On post-map simulati...Question on PCI-express verssus Standard PCI performance [7 articles]
Benjamin Couillard - 2011-07-26 17:14:00
Hi everyone,
I'm working on a conversion project where we needed to convert a PCI
acquisition card to a PCI-express (x1) acquisition card. The project
is essentially the same except instead that ...Issues with Soft-Cores [8 articles]
Slamy - 2011-07-26 01:58:00
Hello.
I'm a little bit tinkering with soft core cpus for fpgas, but I really have
serious issues doing so. Thats why I decided to ask some experts and
register here.
I tried to find a efficient s...synthesizing [4 articles]
ECS.MSc.SOC - 2011-07-25 14:29:00
Hi all
I want to calculate a simple formula, including multiply and division
operands. I use Verilog language to program FPGA.
Can I use the sign of Multiplication (*) and Division (/)? Or I ha...About the setup time of BUFGMUX in Spartan6 [2 articles]
jianhuawow - 2011-07-25 10:29:00
I'm so confused about the setup time of BUFGMUX. In the datasheet of Spartan6, this spec is defined relatively to rising edge.
But if the structure of BUFGMUX is like
http://www.design-reuse.com/...