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Comp.Arch.FPGA
Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.
There are 16329 threads in our archives.
You are looking at page 18 of 1633.
The threads with the newest articles are listed first.
ASM hardware language definition file for Altera/Xilinx [8 articles]
Weng Tianxiang - 2010-01-07 22:46:00
Hi,
I need to write ASM hardware language for circuits. I wrote a lot
about 10 years ago for Altera chip. Now I couldn't find the ASM
hardware language definition file from Altera/Xilinx.
Please...
Video Processing [11 articles]
Ghostboy - 2010-01-07 13:52:00
Hi,
I want to send a video file from a pc to a FPGA (on a XUPV2P development
board) via the PCI interface. On the FPGA the video will be processed by an
algorithm. The result, after processing, wil...ADC problem on spartan3E [8 articles]
mlajevar - 2010-01-07 08:23:00
Hello
I wrote a vhdl code for implementing amplifer and ADC on sparan3E board, I
am working with LTC1407A-1 Dual A/D on spartan3E(with SPI protocol),my
problem is when I changed the analog voltage...Add custom Ip to EDK - No result from sw registers
airol - 2010-01-07 06:12:00
Hello there,
I'm adding custom IP (DCT core) to EDK 9.1. Input (xin) is write to
slv_reg0 while output (dct2d_out) is write to slv_reg1.
I'm following a tutorial from
http://www.ee.cooper.edu/...PMC or XMC based on Altera parts (preferably Stratix) [2 articles]
jfh - 2010-01-07 05:01:00
Hi,
On a project requiring intensive processing based on VXS boards we are
looking at ways of increasing the processing power by using a
mezzanine board hosting a large FPGA with fast access memo...Serial Flash reaches 104MHz Quad IO speeds
-jg - 2010-01-07 00:22:00
MX25U : 1.8V 4-I/O Operating at speeds up to 104MHz of each I/O in 4-
I/O mode, 8Mb-64Mb
This device makes FPGA SoftCPU code problems a little bit easier.
Two of these devices could deliver ...A VHDL compiler error report in Xilinx ISE 10.1 and service pack 3 without response
Weng Tianxiang - 2010-01-06 11:51:00
Hi Xilinx,
Here is the error reporting with its code and compilation result with
ISE 10.1 and service pack 3.
The code is specially simplified to highlight the VHDL compiler error
characteristics....How to protect my Virtex5 design without battery? [12 articles]
vcar - 2010-01-05 12:03:00
For certainreasons, I could not use battery on my board, so the
Virtex5 bitstream encryptioncould not be used. In this situation, what
could I do to protect my design on areasonable level?
My des...EPCS vs SPI Flash [5 articles]
Omer Osman - 2010-01-05 11:14:00
Hello world,
I'm looking at making my first FPGA board with a Cyclone III EP3C25
and am researching my boot memory solution. Reading Altera's docs they
reference their EPCS series serial programm...[Digilab IIE board]Cable autodetection failed [5 articles]
Angus - 2010-01-05 03:00:00
Hi,
I am using ISE 9.1
I had an old Digilab IIE board which i want to use. The Digilab IIE
board can be programmed using the PC's parallel port. However, my PC
has only USB ports. as such i bo...