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Comp.Arch.FPGA
Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.
There are 16714 threads in our archives.
You are looking at page 18 of 1672.
The threads with the newest articles are listed first.
OT and Newbie: SDRAM Auto Refresh [4 articles]
Giorgos Tzampanakis - 2010-06-03 21:12:00
I've been trying to work with an SDRAM chip. I see that I need to
refresh every 64 ms. I can do this using Auto Refresh.
Supposedly, Auto Refresh uses an internal counter to count the
row addr...
ISE Design Suite 11 will not evaluate 2's comp [2 articles]
shannon - 2010-06-03 16:38:00
If anyone out there uses Xilinx ISE Design Suite 11, I need your help!!
According to this information
[link]http://www.fpgarelated.com/usenet/fpga/show/662-1.php[/link]
ISE 11 should be running ...ISE Design Suite 11 will not evaluate 2's comp [2 articles]
shannon - 2010-06-03 15:47:00
If anyone out there uses Xilinx ISE Design Suite 11, I need your help!!
According to this information
[link]http://www.fpgarelated.com/usenet/fpga/show/662-1.php[/link]
ISE 11 should be running ...Job experience? How? [10 articles]
Socrates - 2010-06-03 13:00:00
Hello,
I am a third year student, but interested in FPGAs and linking my future
with this area of electronics. To have a point of view of my future, I've
browsed some job search pages using "FPGA" in...How good are Actel tools [8 articles]
rickman - 2010-06-03 11:51:00
I know Antti has a lot of experience with Actel, so I expect to hear
from him, but I am sure there are others out there with experience of
Actel tools. A customer of mine has told me that he used A...Block RAM unusually long setup time ? [8 articles]
Sharath Raju - 2010-06-03 11:01:00
Hello,
We are working on a project which involves using BLOCK RAMs. Since we
were new to Block RAMs, I (my colleague actually) instantiated a BLOCK
RAM in VHDL using Xilinx's Block RAM IP core.
...Spartan6 power consumption
pes - 2010-06-03 04:51:00
Hi,
Have you got some examples of Spartan6 power consumption betwwen
differents configurations?
Thank you
...Spartan-6 hold time problems (multipost to Xilinx forums) [3 articles]
Rob Gaddi - 2010-06-03 03:53:00
I've got a Spartan-6 design with two different clocks. They're
generated from the same 20 MHz reference on two PLLs, and are called
WB_SYS.CLK_I (50 MHz) and clk128. They're treated as entirely ...Re: Programming Digilent Nexys 2 from Linux [5 articles]
Hauke D - 2010-06-02 23:41:00
A while back, Andy Ross posted a Perl script that pulls together the
many steps required to program a Digilent Nexys2 board under Linux:
http://groups.google.com/group/comp.arch.fpga/browse_thread...Graphical User Interface project on Spartan-3 FPGA [8 articles]
Simon Piekert - 2010-06-02 04:39:00
I am a student of Electronics and I am going to do semester work on the
topic "Implementation of Graphical User Interfaces on an Embedded Platform".
We are allowed to choose a project of our own s...