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Comp.Arch.FPGA

Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.

There are 17402 threads in our archives.

You are looking at page 19 of 1741.

The threads with the newest articles are listed first.

FPGA not getting programmed [17 articles]

salimbaba - 2011-07-25 10:04:00
Hi, I am using a custom board design in which i have 2 FPGAs (spartan 3 xc3s4000) and an EEPROM xcf16p daisy chained together. The chain is like this: EEPROM -> FPGA1 -> FPGA2 Now the problem...FPGA not getting programmed

FSL Problem:Data Return and Use [8 articles]

aibk01 - 2011-07-25 05:33:00
Hi! I wrote a custom IP peripheral in verilog and interfaced it to MicroBlaze, using Harware> Co-processor option. I can see the peripheral connected on the System Design Diagram.All compile a...FSL Problem:Data Return and Use

source synchronous DDR bus with non-continuous clock [9 articles]

fpgaace - 2011-07-22 09:37:00
I'm hoping to get some help/advise on how to design this interface. We're targeting Spartan-6. There=92s a bidirectional, source synchronous, DDR, single-ended bus running at only 25Mhz. The pro...source synchronous DDR bus with non-continuous clock

Speed attained by virtex 6 [3 articles]

Fpga.Dev69 - 2011-07-21 09:56:00
Dear sir, I am working on the virtex 6, XC6VLX550T FF1759 speed grade -1 , using finite state machines with high operands, (113 bits), in Galois field inverse theory. The problem I face is that I ...Speed attained by virtex 6

sdxc

Sk3ptic - 2011-07-19 11:51:00
Anyone familiar with SDXC host controller? I'm not getting the performance I need because I am getting too much delay between writes using CMD25. I'm trying to stream video, do I have to use CMD20 o...sdxc

RTL timing issue [6 articles]

salimbaba - 2011-07-17 05:33:00
Hi, I am using a customized board with 1 spartan 3 xc3s4000 FPGA and 2 Gigabit Phys. My system clock is 125Mhz and i am facing an issue which occurs after a while but since it occurs so it is a prob...RTL timing issue

ASM vs. RAM [6 articles]

dragonfly - 2011-07-15 13:14:00
Hi! Can anyone prompt me what is potential benefit of using of auto-sequencing memory (ASM) instead of standard static RAM? The final interest is ASIC – die size and power dissipation. I’m s...ASM vs. RAM

Area optimization (optimizing DSP48E usage) [2 articles]

Vivek Menon - 2011-07-15 10:28:00
I am trying to map, place & route a large design on a Xilinx Virtex 6 FPGA Target Device : xc6vlx550t Target Package : ff1759 Target Speed : -2 My mapping process fails with the following err...Area optimization (optimizing DSP48E usage)

OT: Fast Circuits [21 articles]

Chris Maryan - 2011-07-15 10:02:00
A coworker and I were debating what do the likes of Intel, IBM and AMD do d= ifferently that allows them to design circuits at 3GHz+. In contrast with F= PGAs which for the most part run on a simila...OT: Fast Circuits

Looking for a FPGA board [17 articles]

Thomas Heller - 2011-07-15 08:07:00
I'm looking for a FPGA OEM module for analog signal processing which contains the following: - medium size spartan 3 or spartan 6 FPGA - 2 ADCs, sampling rate > 50 MHz, at least 14 (better 16) b...Looking for a FPGA board
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