Sign in
Search Comp.Arch.FPGA
fpga by Keywords
Altera | ASIC | CPLD | Cyclone | DCM | DDR | DSP | Ethernet | ISE | JTAG | Linux | LVDS | Microblaze | ML310 | Modelsim | NIOS | OPB | PCI | Quartus | RocketIO | SDRAM | Spartan | Spartan3 | SRAM | Stratix | Verilog | VHDL | Virtex | Virtex-4 | Virtex-II | Xilinx | XST
Ads
See Also
Comp.Arch.FPGA
Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.
There are 16333 threads in our archives.
You are looking at page 19 of 1634.
The threads with the newest articles are listed first.
A VHDL compiler error report in Xilinx ISE 10.1 and service pack 3 without response
Weng Tianxiang - 2010-01-06 11:51:00
Hi Xilinx,
Here is the error reporting with its code and compilation result with
ISE 10.1 and service pack 3.
The code is specially simplified to highlight the VHDL compiler error
characteristics....
How to protect my Virtex5 design without battery? [12 articles]
vcar - 2010-01-05 12:03:00
For certainreasons, I could not use battery on my board, so the
Virtex5 bitstream encryptioncould not be used. In this situation, what
could I do to protect my design on areasonable level?
My des...EPCS vs SPI Flash [5 articles]
Omer Osman - 2010-01-05 11:14:00
Hello world,
I'm looking at making my first FPGA board with a Cyclone III EP3C25
and am researching my boot memory solution. Reading Altera's docs they
reference their EPCS series serial programm...[Digilab IIE board]Cable autodetection failed [5 articles]
Angus - 2010-01-05 03:00:00
Hi,
I am using ISE 9.1
I had an old Digilab IIE board which i want to use. The Digilab IIE
board can be programmed using the PC's parallel port. However, my PC
has only USB ports. as such i bo...Digital-to-Analog Converter LTC 2624, Spartan-3A [7 articles]
m m - 2010-01-04 02:07:00
I would like to know if anyone here has already done a VHDL code to
communicate/give commands to the LTC2624 Digital to Analog Converter
that has the Spartan-3A starterkit board.
I am not asking ...NOR-based Flash Memory - Design [4 articles]
karthikbalaguru - 2010-01-02 14:50:00
Hi
In NOR-based flash memory, once a bit has
been set to 0, only by erasing the entire block
it can be changed back to 1. I am eager
to know the reason for that behaviour/design ?
Further, i wo...Xilinx and Multi-port memories [14 articles]
Rob Doyle - 2010-01-02 11:49:00
I'm trying to build a register-file for an ALU which has 3 read ports
and 1 write port. There is a single clock design but I need to assume
that all ports are in use on every clock cycle, wors...MB debug module
ines_fr - 2010-01-02 07:20:00
I'm working on a multiprocessor architecture targeting spartan 3 starter
kit. (referring to the tutorial XAPP996). I'm stuck in the phase of run
implementation set, because I could not connect the Mic...verilog multiplexer [6 articles]
maxascent - 2010-01-02 05:27:00
I would like to create a generic multiplexer in Verilog were I can set the
number of inputs and data bits. I can create something using 2 input
multiplexers cascaded but this produces a priority struc...VHDL: assignment to two different fields of the record in two different processes [8 articles]
wzab - 2010-01-01 02:58:00
To simplify design of the DSP system I have decided to describe the
ports connecting different blocks (to be synthesized in the same FPGA) as a
record.
It resulted in a code, in which two different...