Sign in
Search Comp.Arch.FPGA
fpga by Keywords
Altera | ASIC | CPLD | Cyclone | DCM | DDR | DSP | Ethernet | ISE | JTAG | Linux | LVDS | Microblaze | ML310 | Modelsim | NIOS | OPB | PCI | Quartus | RocketIO | SDRAM | Spartan | Spartan3 | SRAM | Stratix | Verilog | VHDL | Virtex | Virtex-4 | Virtex-II | Xilinx | XST
Ads
See Also
Comp.Arch.FPGA
Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.
There are 16714 threads in our archives.
You are looking at page 19 of 1672.
The threads with the newest articles are listed first.
Effect of fanout on route delay (Spartan3) [3 articles]
Marc Jet - 2010-05-31 13:23:00
Hi,
The Spartan3 datasheet is very light on the topic of interconnect. I
wonder how big the effect of fanout is, on the delay of a route. I'm
not talking about "high fanout" signals like CLK, b...
Virtex 7? [4 articles]
stephen.craven@gmail.com - 2010-05-31 07:47:00
The CTO of Xilinx, during his keynote this morning at the
Reconfigurable Architectures Workshop in Atlanta, made mention of the
recent announcement of the Virtex 7 architecture. My colleagues and I...MIG v3.0 inputs signal [9 articles]
Eagle_mk4 - 2010-05-31 05:34:00
Hi, I´m using MIG v3.0 to generate the VHDL code for a DDR SDRAM
controller. I implement the design but I don´t know which is the
format(values) the inputs signal, as for example app_af_addr, app_ma...Estimating resource utilization of cores (from Xilinx CoreGen) [4 articles]
onkars - 2010-05-30 15:30:00
Hi,
How can I estimate the resoures used by a core generated by CoRE GEn ---- I
guess the resource utilization report should give this right?
What do the percentages in the resource uti...Last Xilinx Webpack that was big-brother free? [11 articles]
John_H - 2010-05-30 10:27:00
Call me a sadist, but I tend to cruise through the license agreements
and EULAs before installing software to make sure I'm not being
victimized by using someone's application. I wanted to bring my...Advice on Xilinx Spelunking [17 articles]
Rob Gaddi - 2010-05-28 16:45:00
I've got a Spartan 6 design that I'm working with under ISE 11.5. A
code block that I would expect to take up about 200 LUTs is taking 800
instead. 600 LUTs wouldn't be the end of the world, exc...crc16 with 16 bit inputs [11 articles]
bdurr - 2010-05-27 22:58:00
Hello,
I am trying to implement several crc generator/checkers in vhdl in an fpga.
The crc32 seems to work ok, a byte at a time.
Can I do crc16 16 bits at a time, rather than a byte at a time?
...Using XMOS devices to replace FPGAs [5 articles]
Leon - 2010-05-27 14:18:00
Here is a nice paper showing how XMOS devices can replace FPGAs in
many applications:
http://www.xmos.com/system/files/wp-xmos-fpga.pdf
Leon
...Xilinx ISE12.1 IPCORE source code
doomsten - 2010-05-26 23:50:00
1.the format of encrypted file
can_v3_2/can_tl_bsp.vhd as an example.
a)the first 8 bytes XlxV62EB is version code,From ISE11.1 Xilinx use
AES.
b)the first 8bytes of line2 is the length of the cip...how to decrypt Xilinx ISE12.1 IPCORE source code
doomsten - 2010-05-26 23:48:00
1.the format of encrypted file
can_v3_2/can_tl_bsp.vhd as an example.
a)the first 8 bytes XlxV62EB is version code,From ISE11.1 Xilinx use
AES.
b)the first 8bytes of line2 is the length of the cip...