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Comp.Arch.FPGA
Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.
There are 17402 threads in our archives.
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CFP : The 3rd International Workshop on Highly Efficient Accelerators and Reconfigurable Technologies (HEART 2012), Okinawa, Japan, 30 May - 01 June 2012
Khaled - 2012-01-29 09:17:00
************************************************************************
CALL FOR PAPERS
The 3rd International Workshop on
Highly Efficient Accelerat...
Comunicacion tcp/ip matlab
david - 2012-01-28 15:55:00
Hola,
desearia conocer la comunicacion tcp/ip cuales son los comandos o
algun link donde estas sentencias se hayan probado con algun
dispositivo. ojo es en matlab version 7.6
david.samniego@...XLNX efuse anyone? [2 articles]
SysTom - 2012-01-27 04:38:00
(repost from XLNX forum)
Has anyone succesfully managed to program the eFuses? On the Virtex-6
in particular but any device would be good...
There seems to be many restrictions and I am unclear...OT : No daily abridged emails [2 articles]
jozamm - 2012-01-27 03:09:00
Hi all,
I have been a long time member of this group receiving 1 abridged email eve=
ry day. A month ago I stopped receiving it with no reason. I unsubscribed a=
nd subscribed again to the group,...slow edge on clk inputs [6 articles]
Morten Leikvoll - 2012-01-26 20:02:00
Are there any simple practical [fpga internal] solutions to aviod internal
"ringing" on slow (edged) clock inputs on fpga's, other than resampling and
filtering in a different clock domain?
(Usin...FPGA not working after programming from EEPROM [6 articles]
salimbaba - 2012-01-26 17:21:00
Hi,
I am using xilinx spartan 3 xc3s4000 FPGA in my design interfaced with two
gigabit phyters from National and I have xilinx xcf16p EEPROM on board to
program the FPGA.
When I program the FPGA...Semi-OT: Good Tcl Book [5 articles]
Rob Gaddi - 2012-01-24 11:44:00
More and more I find myself needing to write Tcl. My simulator gets far easier to work with if I've got it scripted than going clicking around. Likewise, all of my configuration and control files un...balancing IIR filter (after adding extra registers) [24 articles]
zak - 2012-01-24 02:26:00
I designed a low pass IIR filter in starix iv but I got speed problem. I
need to run it on 245MHz but can only achieve about 180. I was advised by
experts to insert extra registers and this improved s...MicroBlaze MCS Error. [2 articles]
=?UTF-8?B?44OQ44K144Ot?= - 2012-01-23 08:18:00
Hi all.
I'm T.Koyama.
I download ISE 13.4 and make IP Microblze mcs.
I could make IP and bitstream,and I make ELF file under SDK
So I will download to FPGA, but Error ocuuer.
Error meaaseg is...clock enable question [4 articles]
Jim - 2012-01-22 19:13:00
I created the following clock enable block:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity clock_enable is
generic (
OUTPUT_CLOCK_ENABLE_PERIOD : tim...