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Comp.Arch.FPGA


Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.

There are 16714 threads in our archives.

You are looking at page 2 of 1672.

The threads with the newest articles are listed first.

about (low-level) jtag [2 articles]

Me - 2010-08-27 18:29:00
Hi Guys, I'm trying to make a jtag adapter out of an 8-bit micro-controller and a usb-serial adapter. So far, I can connect to my target and read it's IDCODE upon power up, due to it being aut...about (low-level) jtag

Xilinx RocketIO problems [7 articles]

John Stein - 2010-08-27 10:41:00
Hi. I am trying to establish a communication between two RocketIO driven Virtex2P FPGAs. I am currently simulating the design running into the following problem: When I set the RocketIO Transmitter...Xilinx RocketIO problems

Spartan-6 - What is the IODRP2_MCB?? [2 articles]

=?windows-1252?Q?GaLaKtIkUs=99?= - 2010-08-27 09:23:00
Hi, While studying the MIG ref design for Spartan-6 I was surprised to find a IODRP2_MCB which doesn't have any documentation. Any information about it? Thanks ...Spartan-6 - What is the IODRP2_MCB??

Checking whether the client is connected to the Server

micro - 2010-08-27 07:59:00
Hi, I am working on establishing Client-Server module over TCP.I have put a set up such that my PC acts as a normal server where I can connect it from some other PC's on my LAN using 'telnet ipaddre...Checking whether the client is connected to the Server

Differences between Verilog versions [4 articles]

Giorgos Tzampanakis - 2010-08-26 17:09:00
Where can I find a listing of the features that were added to Verilog in the 2001 version, and then of the ones added in SystemVerilog? ...Differences between Verilog versions

New Application Note: Multiple configurations for Altera FPGAs [6 articles]

Bert_Paris - 2010-08-26 09:04:00
Hi, After seeing a number of customers struggling with this issue, I have written a detailed ApNote showing how to implement a multiple configuration system for Altera FPGAs. The example is a C...New Application Note: Multiple configurations for Altera FPGAs

Mismatch between Xilinx FIR interpolation filter [2 articles]

Benjamin Couillard - 2010-08-25 15:31:00
Hi everyone, I'm currently using a design with a 5 /4 interpolation Filter used to convert a signal sampled @ 80 MHz to 100 MHz. The Interpolation filter is designed using FIR compiler 3.2 (ISE 1...Mismatch between Xilinx FIR interpolation filter

Text compression Huffman Encoder and Decoder [10 articles]

kude - 2010-08-24 13:22:00
Hi all, I am working on text Huffman Encoder and Decoder to be implemented on FPGA. and here are things which are not clear for me. 1.Will the binary tree be constructed by software and then the co...Text compression Huffman Encoder and Decoder

Looking to buy some obsolete FPGAs

Jonathan Bromley - 2010-08-24 09:59:00
hi all, I've been helping out a small amateur team who, for reasons that don't concern us here, need to get hold of a few ancient QuickLogic FPGA devices. They have already been cheated by at l...Looking to buy some obsolete FPGAs

Xilinx Xcell Journal Issue 72 Now available [2 articles]

Mike Santarini - 2010-08-24 08:11:00
Hi folks, my team here at Xilinx just published a new issue of Xcell Journal: http://www.xilinx.com/publications/xcellonline/index.htm. This issue has some great tutorial and how-to articles. Check ...Xilinx Xcell Journal Issue 72 Now available
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