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Comp.Arch.FPGA
Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.
There are 16333 threads in our archives.
You are looking at page 2 of 1634.
The threads with the newest articles are listed first.
Modelsim PE vs. Aldec Active-HDL (PE) [38 articles]
Pete Fraser - 2010-03-09 20:27:00
I've finally decided to buy a better simulator
(I've been making do with Modelsim XE so far).
Any thoughts as to the relative merits of Modelsim PE and
Active-HDL (PE) for FPGA simulation?
Tha...
Using the SignalTap Logic Analyzer [2 articles]
pinkisntwell - 2010-03-08 12:34:00
I'm using Quartus and I'm trying to compile a SignalTap Logic Analyzer
file with my project. No matter what I do the only indication I get is
"Please compile the project to continue". I have tried c...Looking for a USB JTAG cable [3 articles]
Jason Thibodeau - 2010-03-07 22:17:00
Hello,
I have a Spartan 3 Starter board. I used to program it with my parallel
JTAG cable, but I now do my implementations on a laptop without a
parallel port. I am in the market for a USB JTAG...Laptop for FPGA design? [22 articles]
Pete Fraser - 2010-03-07 12:03:00
I'm going to be travelling soon, and will continue to
do FPGA design from the road. I'll need to get a
new laptop for this.
Any thoughts?
I think something based on the Core i7-620M might
be fa...Virtex-4 driving a 5V CMOS [7 articles]
fpgauser - 2010-03-07 09:56:00
Hi all,
I need to drive a 5V CMOS input from a 2.5V Virtex-4 bank. Is there anything
wrong with simply using a pullup to 5V? The speed doesn't matter.
Thanks.
...Spartan 3 minimum clock pulse width [2 articles]
Andrew Holme - 2010-03-07 09:13:00
What's the minimum clock pulse width I can drive into a Spartan 3 global
clock input via LVDS? I'm using the -5 speed grade device with VDDC cranked
up to 1.25V. I've currently got it working at...Question in verilog testbench [4 articles]
Frank - 2010-03-07 08:43:00
Hi, all
I have a question in the testbench written by verilog. Why we always
define the inputs of MUT as reg and outputs of MUT as wire, just the
opposite with the in/output definition in verilog...Actel is now the only FPGA vendor with hard-core processor in the latest family [8 articles]
Antti - 2010-03-07 00:12:00
as Xilinx has dropped hard processor IP in the latest families it
makes ACTEL the only FPGA vendor whos latest product family does have
hard processor IP.
Smart fusion includes Cortex-M3, and yes...FSM in BlockRAM [14 articles]
de4 - 2010-03-06 19:09:00
Hello to all !
I've problem with finite state machine. Because I have not much place in my
FPGA and I need to create few more FSM i found that FSM logic can be packed
in to BRAM. I created simple F...Ethernet development kit [5 articles]
Kastil Jan - 2010-03-06 10:20:00
Hi folks,
I would like to ask you for recomandation of the ethernet development kit
with FPGA (much preferably Xilinx's one). Our requirements are the low
power, as big FPGA as possible and at le...