Comp.Arch.FPGA
Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.
There are 17402 threads in our archives.
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Andreas Ehliar - 2011-07-15 02:47:00
A long time ago there was a thread on comp.arch.fpga regarding how to
regularly print out some information about the simulation progress.
The thread was fairly short and no real progress was made to...
chifalcon - 2011-07-14 03:23:00
Hi,
I need to modify the netlist generated from "Generate Post-map simulation
model"(i.e. netgen).
After the netlist modifcation, can I continue the work of place&route
based on the modified ...
Nikolaos Kavvadias - 2011-07-13 13:51:00
Hi everyone
i'm pleased to announce that after two years (and about 2000 man-
hours), the HercuLeS high-level synthesis tool is ready for non-
trivial work. HercuLeS allows you to synthesize ANSI...![[ANN] HercuLeS high-level synthesis tool](http://www.fpgarelated.com/new/images/
icon_more.jpg)
John Adair - 2011-07-13 03:13:00
Two new FPGA coprocessor modules released today. The initial
availability will be modules based on a Xilinx Spartan-6 XC6SLX150
FPGA although we may offer these products with either a XC6SLX45 or
X...
aisitei - 2011-07-12 21:27:00
Hi.
I'm just beginner in making fpga
and i want to make MIPI CSI-2 to parallel converter in fpga.
i think there are strange point.
in mipi spec, there are two mode, LP and HS mode, and these are...
Hello, all,
I am trying to make a counter follow the value of a value sent from another
device. The value coming in is a bidirectional counter that can rollover
in either direction. The value i...
Sink0 - 2011-07-10 11:14:00
Hi need to implement a bidirectional 8 bit interface of a FPGA with a
microcontroller. For now i am developing with a Ciclone II but i will
have to make it for a Spartan-3A too.
Inside the FPGA i...
Mawa_fugo - 2011-07-10 00:54:00
1) Why the spec calls out negative number for input holding time ? eg.
TphDCM = - 0.26 ns
2) What does that means when they say
"When the hold time is negative, it is possible to change the dat...
r_hwdesigner - 2011-07-08 04:28:00
we are looking for an fpga designer in Genova with the following
knowledges:
Operating systems
Windows, Linux
Programming Languages
VHDL, verilog, System Verilog, C++
Tools
FP...
jgk2004 - 2011-07-07 12:19:00
Hello all,
I am presently working with a virtix 5 FPGA and trying to get the rocket
IOs to work with reading in the data generated from my ADC. The ADC is
clocked at 500MHz and I have 5 LVDS output...
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