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Comp.Arch.FPGA
Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.
There are 16714 threads in our archives.
You are looking at page 20 of 1672.
The threads with the newest articles are listed first.
EDK BFM Simulation [4 articles]
maxascent - 2010-05-26 19:21:00
Has anyone managed to get access to the BFM simulation package. For some
reason I keep getting denied.
Jon
---------------------------------------
Posted through http://www.FPGARela...
Help (Virtex 155 and 220 compatibility) ! [2 articles]
Kazu - 2010-05-26 14:22:00
I had a board which mounted Virtex 155. I've changed the FPGA to
Virtex 220.
The support engineer of Xilinx sales company said both FPGAs were
compatible and there was no problem.
But all 4 board...BRAM with output register using ram_style attribute [2 articles]
shantesh - 2010-05-26 06:22:00
Hello,
I'm curious to know if there is a way we could tell the synthesizer to use
registered mode of BRAM when using ram_style "block" attribute.
The registered mode otherwise can be en...Xilinx Xact software for XC2018 Logic Cell Array [18 articles]
rombios - 2010-05-25 17:17:00
I bought a few of these on ebay but I cant find Xilinx Xact software
needed to design with these FPGAs
Can someone point me in the right direction?
Anyone have a copy I can buy?
sincerely
...mux behavior [11 articles]
hssig - 2010-05-25 16:22:00
Hi,
how does an (unclocked) 2:1 multiplexer behave if input B is selected
and input A becomes metastable ? Does the metastability of A have an
influence on the stability of the mux output at any ...Debugging SDRAM interfaces [16 articles]
Philip Pemberton - 2010-05-24 10:17:00
Hi guys,
I could really use some help from an SDRAM / FPGA guru here...
I've got an SDRAM controller IP core -- specifically, the sdram_wb core
by Stephen Williams, available from the Git reposi...About CLB inter-slice communication in Virtex [2 articles]
null - 2010-05-24 07:48:00
In the Virtex 4 FPGA, slices within a CLB are interconnected with each
other. However, in Virtex 5 and Virtex 6, there is no direct connection
between slices of a CLB. Why was this change made?
Tha...spartan6 configuration [2 articles]
pes - 2010-05-23 23:22:00
Hi all,
In my Spartan6 board design, I want to use a Xilinx platform flash to
configure it.
My Spartan6 is a XC6SLX150 (32.2Mbits configuration memory) and the
flash is a XCF32P (32Mbits).
...Do Xilinx really want people to report INTERNAL_ERRORs? [2 articles]
Philip Pemberton - 2010-05-23 20:05:00
... because it certainly seems like they don't.
A couple of minutes ago, I made some changes to my project which made the
synthesizer fall flat on its face:
INTERNAL_ERROR:Xst:cmain.c:3464:1.5...can I do image processing using 8bit color output FPGA board? [2 articles]
Gladys - 2010-05-21 21:58:00
Hi, I have a Spartan 3E FPGA starter board of 100K gates. I just want
to do some basic image processing such as dead pixel correction(I just
use black&white images), there is only 8 bits color outpu...