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Comp.Arch.FPGA

Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.

There are 17402 threads in our archives.

You are looking at page 21 of 1741.

The threads with the newest articles are listed first.

Verilog Custom Core To Read and Write From RAM [9 articles]

aibk01 - 2011-07-07 12:15:00
I want to add a custom verilog core to an already established pipeline of microblaze. The core should be able to read data from memory locations from DDR RAM (external) which is already present on PL...Verilog Custom Core To Read and Write From RAM

What's the black and while round on FPGA slice? [2 articles]

chifalcon - 2011-07-06 10:49:00
Hi, I implemented a full combinatinal logic in Xilinx FPGA. A white and black eye appears on each SLICE. What does it means?? Thanks --------------------------------------- Pos...What's the black and while round on FPGA slice?

Delta-Sigma in an FPGA [9 articles]

Rob Gaddi - 2011-07-05 20:00:00
Hey all -- So I've got yet another project making me say "Gosh it'd be nice to be able to implement a DAC/ADC directly in the FPGA." And so I looked around and found all the same white papers ...Delta-Sigma in an FPGA

small size SDSL modem

bhatti - 2011-07-03 12:40:00
Hi all Can any one kindly tell me from where i can get small size (atleast width < 50mm) SDSL modem with ethernet input? Best Regards --------------------------------------- Post...small size SDSL modem

digitization of sensor array [4 articles]

bhatti - 2011-07-03 03:34:00
Hi all I need to digitize a 32 channel sensor array, hosed in a pipe of 50mm diameter and 6m length. Sensors are hydrophones integrated with preamplifiers. Simultaneous sampling is required with 20...digitization of sensor array

verilog task and vhdl [11 articles]

carlob - 2011-07-01 05:30:00
Hi all, I've a functional model of a PHY chip in verilog with a lot of tasks to stimualte change on signals at the interface (and not only)... Unfortunately I'm not experienced with verilog...I woul...verilog task and vhdl

Ericsson Eurocom D1

salimbaba - 2011-06-30 15:15:00
Hi, I know this isn't the right place to ask this question, but since i use this forum frequently, i thought i should start from here. Has anybody here worked on Ericsson's Eurocom D1 protocol ? ...Ericsson Eurocom D1

JESD204A and Spartan-6 GTPs

YH - 2011-06-29 10:59:00
Hi, I read the application note “Virtex-5 FPGA Interface to JESD204A Compliant ADC”. I’m designing a pcb with a JESD204A NXP DAC linked to Spartan-6 GTP Dual tiles. I try to know If I...JESD204A and Spartan-6 GTPs

Sporadic simulation result with modelsim [21 articles]

JB - 2011-06-27 07:49:00
Hello all, I struggle with an issue I can't understand the root cause. When simulating my back annoted design with modelsim, I get unexpected behavior when using a simulation step of 1ns, but n...Sporadic simulation result with modelsim

Depth of logical Circuit [8 articles]

Richard - 2011-06-24 23:33:00
Hi all, I sythesised (with Xilinx ISE) some complex logic circuit just consisting of AND and XOR gates and I am wondering if there is any way I can identify in the post-sythese report the depth o...Depth of logical Circuit
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