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Comp.Arch.FPGA
Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.
There are 17402 threads in our archives.
You are looking at page 22 of 1741.
The threads with the newest articles are listed first.
Determine latency of GTX links vs Aurora+LVDS [4 articles]
Vivek Menon - 2011-06-24 03:11:00
I have a design partitioned over 2 FPGAs. I am trying to determine the bene=
fits of selecting GTX links vs. LVDS to transfer the data between FPGAs.
=20
Target Device : xc6vlx550t
Target Package...
Xilinx or Altera [16 articles]
Simon - 2011-06-22 12:15:00
Hopefully not sparking any religious wars here, but hoping for some
advice from those-who-know :)
I switched to using Altera's software a couple of years ago, because
it felt more intuitive to me...How to open the interface GUI of ChipScope Pro Analyzer on linux [3 articles]
Amy_jing - 2011-06-21 16:55:00
Hi,
I want to using ChipScope Pro Analyzer to check my design. I have already
generated the icon and ila cores and connected them with my design. But I
am stumbled with how to open the interface GU...AVI container and VGA display [2 articles]
tandt_53 - 2011-06-21 14:34:00
hi all!
I'm working on the Spartan 3E started with mapping MJPEG decoder. I had the
source code of the JPEG deccoding, now I use AVI container to display MJPEG
via VGA port. I wanna find the first i...ucf file for 32 bit counter spartan 3e S500E -4 [3 articles]
moudud - 2011-06-21 14:06:00
I have designed a 32 bit counter but I am having a difficulty in assigning
32 pins to the 32 bits since I don't know the "LOC" (location) of the pins
which is required in the User Constraints file.
I...Xilinx ISE ignores Max Fanout
submachine - 2011-06-21 07:56:00
I had been working with Xilinx ISE 12.4 for a while trying to improve the
performance of a SPARC based processor.
Till now, I was always and stopping at the "Synthesize - XST" step. I found
that go...[OT] How to save an artifical life..
DavCori - 2011-06-21 06:45:00
Hi everyone,
I would like to share a youtube clip...one click costs nothing while can
save lives sometimes (expecially mine).
http://www.youtube.com/watch?v=PiCeqtGHpJI
Thanks a lot and cheer...Choosing a scope [5 articles]
scrts - 2011-06-19 11:18:00
Hello,
I am trying to choose a new oscilloscope, but also keeping my eye on logic
analyzers. I am mostly working with video stream over FPGA, so I need a
scope for this purpose. I've narrowed my ...Area Optimization [25 articles]
Christopher Head - 2011-06-17 20:59:00
Hi all,
I have a design (written in VHDL) targetting the Spartan 6 series, and
it's oversubscribed for LUTs. Can anyone recommend good resources to
read? I've already spent a little time looking ar...FFT using logic gates only [10 articles]
moindsp - 2011-06-17 11:07:00
I intend to implement FFT using Logic gates only , by this i mean i
have written verilog code of FFT for xilinx spartran III, I can
visualize it in Xilinx ISE 13.1 using technology schematic. But it...