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Comp.Arch.FPGA
Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.
There are 17402 threads in our archives.
You are looking at page 23 of 1741.
The threads with the newest articles are listed first.
Strategic HR Summit 2011 (Jun 25, Mumbai)
shri nidhi - 2011-06-16 00:44:00
Hi There,
I got to know of an exciting event happening in Mumbai on June 25th
I guess it will add a great value to all the HR professionals,
The =93Strategic HR Summit=94 will highlight th...
Strategic HR Summit 2011 (Jun 25, Mumbai)
shri nidhi - 2011-06-16 00:43:00
Hi There,
I got to know of an exciting event happening in Mumbai on June 25th
I guess it will add a great value to all the HR professionals,
The =93Strategic HR Summit=94 will highlight th...multiplication in indexation [4 articles]
kclo4 - 2011-06-11 04:15:00
Hello everyone
I want to do a for loop in order to repeat the same construction and
use the number of the loop to create the index to take the desirated
part of the bus , the problem is that i do...Variable Optimized Away [6 articles]
Calvin Ball - 2011-06-10 10:53:00
Hello,
I am having a problem where Xilinx ISE is trimming away a variable
that I need, tempShifts. I can still implement the module but I am not
sure what it is doing with my variable. This says to...Best syntheses [17 articles]
Michael - 2011-06-07 11:50:00
Hi,
I have been using Xilins XST for a while and have come to a performance
problem which leads me to think of if there is any better syntheses like
Synopsys or other.
The device is a Sparta...Looking for bitgen Virtex7 and Kintex7 support [4 articles]
Neil Steiner - 2011-06-04 17:22:00
Hello,
It appears that bitgen in ISE 13.1 supports Virtex7 and Kintex7
implementation up to but not including bitstream generation. Does
anybody know when bitgen support may be expected for th...How could I get LUT-level netlist in Xilinx ISE? [8 articles]
chifalcon - 2011-06-03 10:23:00
Hi, I need to convert the high level design to LUT level netlist, and then
make corrections to it.
In a paper, author says:
"The translate step generates a Verilog netlist that can easily be pa...Microblaze and PowerPC [4 articles]
am85 - 2011-06-03 05:12:00
Hi,
I would like to perform mathematical operations as Division and Square
root. From what i have read, i either need to use Microblaze or PowerPC.
can anyone please tell me the difference in per...Connecting of IP core simulated in GHDL to pseudoterminal via UART-like interface [3 articles]
Wojciech M. Zabolotny - 2011-06-02 14:41:00
When working with simulated soft CPUs to be implemented in FPGA,
I often needed a possibility to connect terminal emulator
(e.g. Minicom) or my own program to serial port of the simulated
IP core.
...J1 forth processor in FPGA - possibility of interactive work? [17 articles]
wzab - 2011-06-02 13:56:00
Hi,
I'm very impressed with a J1 forth processor: http://excamera.com/sphinx/fpga-j1.html
I'd like to use it to implement simple non-time critical control and
debugging layer
in my FPGA based DS...