Comp.Arch.FPGA
Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.
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Mawa_fugo - 2010-05-14 12:32:00
Hi all,
Which one's better to invest in the next project ?
TIA and TGIF
;-)
...
he - 2010-05-14 06:50:00
Hello,
I had a look into the V6 Datasheets, but couldn't find a direct clue.
Would it be possible to implemement two PCIe Endpoints in one Virtex-6
FPGA? Most of the V6-Devices offer two hard PCI...
Mike Santarini - 2010-05-13 19:34:00
My small but mighty team has recently issued two new issues of Xcell
Journal magazine. The first is our 2010 Customer Innovation issue of
Xcell, which features profiles of 20 customer designs. The l...
rickman - 2010-05-13 01:17:00
I think I have about had it with VHDL. I've been using the
numeric_std library and eventually learned how to get around the
issues created by strong typing although it can be very arcane at
times....
smart0604 - 2010-05-12 06:34:00
I used the simple dual port ram in quartus with the altera fpga,but when i
simulate it in 100Mhz, the read data isn't what i haved writen in. but the
classic timing analyzer shows the fmax is about 20...
m.khairy - 2010-05-11 14:57:00
Hi all
i'm suing ISE 11.4 and ModelSim XE III when i do the behavioral simulation
it works well but when i do the post place & route simulation the ModelSim
report this errors
"# ** Error: netgen/pa...
Eric - 2010-05-10 10:01:00
Hi,
Does someone have some benchmarks comparing the compilation time
between the Windows 64b and Linux 64b editions of the Xilinx ISE
Design Suite? I need some arguments to invest in the right de...
luudee - 2010-05-10 05:29:00
Does anybody else, besides xilinx, make FMC boards for ml605 & sp605 ?
HW-FMC-XM105-G FMC XM105 DEBUG CARD
HW-FMC-XM104-G FMC CONNECTIVITY MEZZANINE CARD
Buying Xilinx products now means goin...
jogendersaini - 2010-05-09 18:26:00
Hello,
I am working on Vertex-5 and i have made a 20-bit counter.
i have taken
signal counter : std_logic_vector (19 downto 0)
Output of the counter is monitored on scope with pre-specif...
jmariano - 2010-05-09 16:49:00
Dear all
Here's my problem: I've developed an VHDL IP in ISE and integrate it
into a Microblaze peripheral using the "create and import peripheral"
tool. My IP uses 3 read only and one write onl...
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