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Comp.Arch.FPGA
Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.
There are 17402 threads in our archives.
You are looking at page 24 of 1741.
The threads with the newest articles are listed first.
Random Reset calls [2 articles]
RSGUPTA - 2011-06-01 10:14:00
Hi Folks,
Need something interesting in random reset:
I am having a testbench in verilog which needs to hit the state
machines states with reset.
Basic Format of testbench:
##############3
ini...
Why feedback clock in SDRAM controllers? [12 articles]
valtih1978 - 2011-05-30 13:28:00
I see it in many SDRAM controllers, e.g.
ftp://ftp.xilinx.com/pub/applications/xapp/xapp608.pdf, and nobody explains
WHY
The extranal feedback trace must equal to CK len. Ok. This means that SD...Package constants (VHDL) [3 articles]
Fred - 2011-05-30 11:39:00
Historically I have used a VHDL file to embody the constants in a
design where possible using meaningful names which can be easily
changed.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package co...Instantiation of an EDF netlist within a Verilog top RTL [3 articles]
rahul_fpga - 2011-05-30 03:25:00
Hello Guys,
I am working with Synplify Pro. I have a RTL wrapper in Verilog where a
module is instantiated. But this module is available as an EDF netlist. How
can I include this EDF netlist in my ...Fall Times and Pullup [10 articles]
shyam - 2011-05-29 00:35:00
If on a bidirectional bus, if there is a strong pull up and there is a
device which is drives the line low, can we reduce the fall time
substantially, if we reduce the pull up on the lines?
Or is...Scoping a glitch [24 articles]
Mr.CRC - 2011-05-27 09:42:00
Hi:
Today I took scope shots of a clock input to my Xilinx Spartan 3e,
Digilent NEXYS2 board. The clock goes to a counter, simulating a
quadrature encoder, as explained in post "Counter clocks o...PCI Express Cable [11 articles]
John Larkin - 2011-05-26 16:50:00
Hi,
Does anybody here have experience designing something to do PCIe over
cable? I need to design (ie, draw the schematic of) a target device
that will have a Molex cable/connector coming in, som...Records as ports in Synplify
mcholbi - 2011-05-26 09:46:00
We are trying to implement a toplevel module which has an IN and an OUT
port which are records. The synthesis works fine but we have the problem
that synplify converts these record ports in a big port...Verify failed between address 0x80000 and 0x8FFFF [7 articles]
harishac - 2011-05-25 18:44:00
Hello,
I've been attempting to basically run through the mem_test template and
tutorial,on Cyclone® III EP3C120 chip board.
I am able to compile the custom SOPC design, the encompassing Quartus...Problem with Xilinx 10.1 PowerPC simulator [3 articles]
Grzegorz Plywacz - 2011-05-24 14:14:00
Hi,
I'm trying to use Xilinx 10.1 SDK for PowerPC simulation. However for =
unknown reasons SDK is unable to connect to debugger. This is a dump =
from XMD console:
Accepted a new TCLSoc...