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Comp.Arch.FPGA


Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.

There are 16726 threads in our archives.

You are looking at page 24 of 1673.

The threads with the newest articles are listed first.

Altra mega core SDI vs. Gennum devices

Mawa_fugo - 2010-05-14 12:32:00
Hi all, Which one's better to invest in the next project ? TIA and TGIF ;-) ...Altra mega core SDI vs. Gennum devices

Two PCIe Endpoints in one Virtex-6? [4 articles]

he - 2010-05-14 06:50:00
Hello, I had a look into the V6 Datasheets, but couldn't find a direct clue. Would it be possible to implemement two PCIe Endpoints in one Virtex-6 FPGA? Most of the V6-Devices offer two hard PCI...Two PCIe Endpoints in one Virtex-6?

2 New issue of Xcell Now available

Mike Santarini - 2010-05-13 19:34:00
My small but mighty team has recently issued two new issues of Xcell Journal magazine. The first is our 2010 Customer Innovation issue of Xcell, which features profiles of 20 customer designs. The l...2 New issue of Xcell Now available

I'd rather switch than fight! [131 articles]

rickman - 2010-05-13 01:17:00
I think I have about had it with VHDL. I've been using the numeric_std library and eventually learned how to get around the issues created by strong typing although it can be very arcane at times....I'd rather switch than fight!

what is the fmax of the simple dual port ram in the altera fpga [3 articles]

smart0604 - 2010-05-12 06:34:00
I used the simple dual port ram in quartus with the altera fpga,but when i simulate it in 100Mhz, the read data isn't what i haved writen in. but the classic timing analyzer shows the fmax is about 20...what is the fmax of the simple dual port ram in the altera fpga

ModelSim XE III error

m.khairy - 2010-05-11 14:57:00
Hi all i'm suing ISE 11.4 and ModelSim XE III when i do the behavioral simulation it works well but when i do the post place & route simulation the ModelSim report this errors "# ** Error: netgen/pa...ModelSim XE III error

FPGA Compilation Time Windows vs Linux [14 articles]

Eric - 2010-05-10 10:01:00
Hi, Does someone have some benchmarks comparing the compilation time between the Windows 64b and Linux 64b editions of the Xilinx ISE Design Suite? I need some arguments to invest in the right de...FPGA Compilation Time Windows vs Linux

FMC Boards ? [12 articles]

luudee - 2010-05-10 05:29:00
Does anybody else, besides xilinx, make FMC boards for ml605 & sp605 ? HW-FMC-XM105-G FMC XM105 DEBUG CARD HW-FMC-XM104-G FMC CONNECTIVITY MEZZANINE CARD Buying Xilinx products now means goin...FMC Boards ?

repeting outputs of counter [2 articles]

jogendersaini - 2010-05-09 18:26:00
Hello, I am working on Vertex-5 and i have made a 20-bit counter. i have taken signal counter : std_logic_vector (19 downto 0) Output of the counter is monitored on scope with pre-specif...repeting outputs of counter

I hit the wall

jmariano - 2010-05-09 16:49:00
Dear all Here's my problem: I've developed an VHDL IP in ISE and integrate it into a Microblaze peripheral using the "create and import peripheral" tool. My IP uses 3 read only and one write onl...I hit the wall
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