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Comp.Arch.FPGA

Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.

There are 17402 threads in our archives.

You are looking at page 25 of 1741.

The threads with the newest articles are listed first.

comparator fast implementation [6 articles]

salimbaba - 2011-05-24 07:36:00
Hi, In my design i have two counters, a write_counter and a read_counter, both are 11 bits wide. I used a simple compare equation like this: assign last_byte = odd_number_bytes ? (read_counter + 2...comparator fast implementation

Quadrature Modulation Tutorial [3 articles]

brent - 2011-05-23 19:25:00
I have made a tutorial using flash programs that will help you understand how quadrature modulation and quadrature demodulation works. It is located here: http://www.fourier-series.com/IQMod/i...Quadrature Modulation Tutorial

Can a glitch-free mux be designed in an FPGA? [8 articles]

Mr.CRC - 2011-05-22 18:11:00
Hi: The simplest incarnation of a 2-to-1 multiplexer can be described by the equation: y = ~s & a | s & b where 'y' is the output, 's' is the select input, with 'a' and 'b' the data inputs....Can a glitch-free mux be designed in an FPGA?

Problem with xilinx 12.3 Timing Analyzer

salimbaba - 2011-05-20 12:56:00
Hi, I am using xilinx 12.3 for my synthesis and implementation. I am having issues running timing analyzer, the problem is that when i run timing analyzer from the ISE Design Tools menu as a stand ...Problem with xilinx 12.3 Timing Analyzer

Counter clocks on both edges sometimes, but not when different IO pin is used [22 articles]

Mr.CRC - 2011-05-19 00:54:00
Hi: I'm using a Xilinx Spartan 3E FPGA (on the Digilent NEXYS2 500k board) to implement a quadrature encoder simulator, among other things. The qep_sim.v code is shown below. The clock input t...Counter clocks on both edges sometimes, but not when different IO pin is used

Modelsim [6 articles]

maxascent - 2011-05-18 17:57:00
Does anyone know if its possible to change the waveform signals so that they are in hex instead of binary. I dont want to do it manually but just have it come up in hex when the design is loaded. T...Modelsim

Random behavior of xilinx simple dual port block ram [3 articles]

salimbaba - 2011-05-18 10:12:00
Hi, I am using xilinx 12.3 for synthesis and implementation of my design and i am facing 2 problems. I don't know if anyone else has faced them or not. Problem 1: I am using xilinx simple dual po...Random behavior of xilinx simple dual port block ram

Soft Processors and Licensing [14 articles]

Alexander Kane - 2011-05-16 17:37:00
Just a bit about the project I'm working on: Have an FPGA gathering and manipulating data, and we need a processor to run the show and to send the data over a network. At the moment we are planning...Soft Processors and Licensing

spartan 3a ethernet [2 articles]

alasli - 2011-05-15 10:06:00
for this project, http://www.fpga4fun.com/10BASE-T.html what things need to be changed in order to make it work in spartan 3a? regards --------------------------------------- Po...spartan 3a ethernet

DDR SDRAM Configuration problem on XUPV2P

kensvebary - 2011-05-12 12:02:00
Hi! So, I'm using XUPV2P board (http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,794&Prod=XUPV2P). And I'm having a problem setting up my DDR SDRAM module to work properly (it never ...DDR SDRAM Configuration problem on XUPV2P
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