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Comp.Arch.FPGA

Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.

There are 17402 threads in our archives.

You are looking at page 28 of 1741.

The threads with the newest articles are listed first.

Xcell Journal issue 75 now available

Mike Santarini - 2011-04-29 12:24:00
We've now published the spring 2011 edition of Xcell Journal (issue 75), which a cover story on Xilinx's new Zynq-7000 EPP family (boots from an ARM Cortex A9 MPU core) and several great features in...Xcell Journal issue 75 now available

Xilinx ML605 Demo Qusstion [13 articles]

Pete Fraser - 2011-04-28 19:42:00
I just took delivery of an ML605, and tried out the demo to make sure the board was OK. The pre-built demo is supposed to allow you to load images, and view them on the DVI or VGA output, while op...Xilinx ML605 Demo Qusstion

Ethernet MAC on Virtex 4 [9 articles]

hassoo - 2011-04-27 19:10:00
Hi all, I am new to the world of FPGA. I want to communicate my Virtex 4 XC4VSX35 FPGA to PC using Tri-mode Ethernet MAC IP core. Please give me any suggestion how to start... Also recommend some ...Ethernet MAC on Virtex 4

Excess Stratix IV and SIII parts inventory [4 articles]

poet_neel@yahoo. - 2011-04-27 12:29:00
Me and some engineers run an FPGA prototyping company. The recent unfortunate disaster in Japan has thrown off our immediate forecasts, we have some left over inventory of SIV 230GX and SIV parts. Thi...Excess Stratix IV and SIII parts inventory

Help with good verilog practices

Sink0 - 2011-04-27 11:20:00
Hi, i have written the following verilog code. Its basically a WB master to read and write from OC PCI bridge core. Can you guys point me what is "ugly" on my code, or what is a bad practice? I j...Help with good verilog practices

advice needed for FPGA chip selection [8 articles]

Manusha - 2011-04-27 08:06:00
Hello, I am working on a project which involve interfacing with Ethernet, USB, SATA and couple of other chips (mostly high performance audio/ video decoders and HDMI transmitters). In addition, t...advice needed for FPGA chip selection

VHDL design and System Verilog testbench [2 articles]

rittu - 2011-04-27 02:57:00
Hello Everybody, I am a verification trainee at a company and i am verifying a design made in VHDL through a Systemverilog testbench.There are some paramters used in the design a...VHDL design and System Verilog testbench

EDK - program behavior [4 articles]

Tobias Baumann - 2011-04-26 13:29:00
Hi Last time I asked something about max array size. Now I have another problem and I think it has also to do with the memory. When I have a bigger program, sometimes it run how I want. But if...EDK - program behavior

SAP training videos [3 articles]

Pooja - 2011-04-25 08:39:00
Hi, Guys, i bought the FICO training videos on sapjuice.com and to tell you the truth they have done a wonderful job creating these videos based on the true sap concepts. The way the training goe...SAP training videos

XST - timing constraints of the combinatorial logic [5 articles]

lyo34 - 2011-04-23 03:29:00
Hello, I am dealing with some issues with timing delays.I would like to know how to implement timing constraints for combinatorial nets in a simple way. For example: an AND gate with two ...XST - timing constraints of the combinatorial logic
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