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Comp.Arch.FPGA
Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.
There are 17402 threads in our archives.
You are looking at page 29 of 1741.
The threads with the newest articles are listed first.
Free Model Foundry USB3300 [11 articles]
carlob - 2011-04-22 18:06:00
Hi all,
I've downloaded from the site in object a model of a usb3300 chip (usb2.0
otg transceiver) because I wanted to simulate the behaviour....I'm trying
to develop an ulpi wrapper and have a behav...
NibzX7 processor [20 articles]
jacko - 2011-04-22 02:22:00
Well, finally got Altera Quartus 10.1 working on Jolicloud linux using the =
dash-> bash hack. The compile speed on this netbook is quite good compared t=
o the old windows box. I've fiddled with th...Help with Assinc counter [4 articles]
Sink0 - 2011-04-21 04:17:00
Hi, i need to use an package counter to check how many packages are
inside a dual port FIFO. The counter should increment the counter at
the posedge of one port and decrement with posedge of another...Help with Verilog Code [4 articles]
Sink0 - 2011-04-19 16:25:00
Hi, i have a very weird behavior on a Veriglog code and i need some help.
Just a fast exaplanation. It is a Wishbone master that should perform N
reads, and the number N is defined by a number that...iir filter [8 articles]
francesco_pincio - 2011-04-19 14:13:00
Hello!
I'm new in the forum and just done an FPGA university course, very very
small...we have only turned on/off led with finite state machine and so
on...now i'm tryng to develope an IIR filter wit...ethernet core on FX12 mini module [4 articles]
bhatti - 2011-04-19 09:00:00
Hi
we have an 10/100Mbps ethernet core (from Opencore) and we have run this
core successfully on Spartan 3E kit. Now we need to shift to another
platform i.e. Virtex-4 FX12 mini module (due to small ...[MODELSIM] How to add signals to wave which is a child of the module being tested? [4 articles]
John Smith - 2011-04-19 05:23:00
Hello:
So I have a separate modules foo (with signals: foo_a, foo_b, foo_c)
and have another module foo1 (with signals: foo_x, foo_y, foo_z) which
instantiates foo within its module.
Now when ...Oscilloscope recommendations Ghz range? [17 articles]
Morten Leikvoll - 2011-04-19 02:38:00
Im looking for an analog oscilloscope in the 2Ghz+ analog bw range and
wonder if you have any experience to share. Im used to the infiniium 54825,
but want to go faster (but not spend a fortune on...IEEE standardization of test data register (TDR) interfaces
Heiko Ehrenberg (GOEPEL) - 2011-04-18 17:09:00
The IEEE P1149.1.1 working group (http://standards.ieee.org/develop/
project/1149.1.1.html) is looking at standardizing test data register
(TDR) interfaces.
The group is looking for participation b...Simili [3 articles]
Rick - 2011-04-18 16:18:00
Still lost in the woods.
I came across the Simili download so I searched the newsgroup. Hasn't
been a post in the newsgroup for 3 years. Is there a fatal flaw of
some kind with this software that...