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Comp.Arch.FPGA
Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.
There are 17402 threads in our archives.
You are looking at page 3 of 1741.
The threads with the newest articles are listed first.
Xilinx virtex-5 pitfalls [3 articles]
Finn S. Nielsen - 2012-01-20 21:30:00
Hello People.
Thought I'd share with you, the latest harvest of pitfalls when using
xilinx virtex-5 (FX) FPGAs. Pitfalls that makes the difference between a
prototype and reliable product.
1...
What is value of scale_sch for FFT5.0 IP core for IFFT
varun_agr - 2012-01-20 05:45:00
We are using scaling in FFT5.0 IP Core for 64 transform size,radix 2
burst mode,natural order,scaling(so get same o/p size as i/p size), i/p
data 8 bit and expected o/p data also 8 bit. For this we ...Compatible Xilinx USB Cables: worth to bother? [26 articles]
Giuseppe Marullo - 2012-01-19 19:11:00
Hi,
I see on Ebay cheap USB Cables(40-60USD) that claims to be compatible
with the Xilinx ones. I don't understand wich one, if any, they emulate
(DLC9G).
Do they work? Are they supported on l...VCD to power consumption trace [3 articles]
Martin Klein - 2012-01-18 11:19:00
Hi all,
I have captured the toggle counts of my design in a VCD file and I
wonder if there are now any tools available that
allow me to plot a nice estimate of the dynamic power consumption of
...ABEL to VHDL/Verilog converter [3 articles]
ksheik.abdul - 2012-01-18 11:07:00
Hi,
where i can get the tool to ocnvert ABEL HDL to VHDL/verilog converter.
Thanks & Regards,
sheik
---------------------------------------
Posted through http://www.FPGARela...Effective square root algorithms implemented on FPGAs already [9 articles]
dpetrov - 2012-01-16 16:36:00
Hello guys,
I'm trying to find a little bit more information for efficient square root
algorithms which are most likely implemented on FPGA. A lot of algorithms
are found already but which one are ...Virtex 5 GC clock pin vs GC//CC clock pins [2 articles]
Michael - 2012-01-13 18:22:00
Hi,
What is the difference between a GC clock pin and a GC/CC clock pin(I
dont mean a CC pin I mean a GC/CC pin)?
Such as below for a V5 xc5vlx50t, package ff665,
AB14|adc2_dco_p|IOB|IO_L7P...Can't get the Xilinx cable drivers installed on SL6.1 (RHEL 6.1) [7 articles]
General Schvantzkoph - 2012-01-12 08:12:00
Has anyone been able to get Impact or Chipscope working on SL6.1/CentOS6/
RHEL6?
It failed with the xsetup GUI but it only gave a useless error message
that it failed in the log.
When I tried...Trying to select a development board, can somebody help me make an informed choice? [6 articles]
chthon - 2012-01-12 07:49:00
Hello,
I am trying to decide what board to order for a project I want to do betwee=
n April and June in school, and for other projects, mainly to exercise VHDL=
and design interesting projects. ...Xilinx SRAM clock-to-out and input constraint with forwarded clock [2 articles]
Sylvain Munaut
Hi,
I have SRAM connected to a FPGA.
The clock is forwarded to the SRAM by the FPGA (using ODDR trick).
The input clock to the system is of another frequency and is
internally multiplied by a DC...