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Comp.Arch.FPGA


Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.

There are 16329 threads in our archives.

You are looking at page 3 of 1633.

The threads with the newest articles are listed first.

FPGA platform?? [13 articles]

JuNNi - 2010-03-04 14:14:00
Hi, I am a beginner at FPGA. I had a query that which platform is used for professional digital designs. Is it linux or windows?? --------------------------------------- Posted thro...FPGA platform??

Antti.... [2 articles]

Nial Stewart - 2010-03-04 13:54:00
I've just noticed and read the thread you started just before Christmas about your Fifo problem. You said... > problem fixed! > solution and explanation in the next Brain issue > (I will...Antti....

Using bidirectional pins in Verilog [2 articles]

Giorgos Tzampanakis - 2010-03-03 15:17:00
I'm trying to use bidirectional pins in Quartus with Verilog. What's the correct way to do it? Altera has some example code: http://www.altera.com/support/examples/verilog/ver_bidirec.html But...Using bidirectional pins in Verilog

Xilinx IOBUF - operation Q (virtex4 chip) [3 articles]

Hunter - 2010-03-03 15:03:00
Hi All, I got this newbie Q I hope to get answer for. I'm looking at some example code sent to me by outside contractor, the code makes use of inout ports of the FPGA: -- begin quote IOBUF1...Xilinx IOBUF - operation Q (virtex4 chip)

Xcell Journal Issue 70: FPGAs in the TV Broadcast market

Mike Santarini - 2010-03-02 16:47:00
Hi folks, we just published the winter issue of Xcell Journal: http://www.xilinx.com/publications/xcellonline/index.htm. This one has a lot of great how-to content including part 1 of a piece on How...Xcell Journal Issue 70: FPGAs in the TV Broadcast market

Spice simulation of IBIS details - model examples [12 articles]

-jg - 2010-03-02 14:25:00
As a simple exercise, I looked at the info in a IBIS file, which is quite simple : V-I tables, and pF and nS values for ramps. So if you have a simple problem : What clock edge should I finally...Spice simulation of IBIS details - model examples

Help with avoiding ground-loops on my PCB+external [8 articles]

digitaljanitor - 2010-03-02 12:23:00
All, Apologies for the cross-post, I know a lot of people who deal with FPGAs are also experts with PCBs, stack-ups, high-speed layout, hoping for some good ideas from both groups. I'm not an ex...Help with avoiding ground-loops on my PCB+external

LVDS i/o in a SystemVerilog Interface block [3 articles]

fpgabuilder - 2010-03-02 11:53:00
I need to instantiate LVDS interfaces in my top-level. I am planning to use SV interface blocks. Altera's documentation suggests that LVDS i/os should only be instantiated using a megafunction. B...LVDS i/o in a SystemVerilog Interface block

Frustration with Vendors! [39 articles]

rickman - 2010-03-02 05:21:00
Sometimes vendors act like they don't want you to use their parts. I am looking for rise/fall time information on an FPGA output in one voltage mode LVCMOS33 and the various drive and slew rate opt...Frustration with Vendors!

Need support for differential 1.2V IOStandard on Virtex-6

Shant - 2010-03-01 21:53:00
Hi all, I'm designing an LPDDR2 SDRAM memory interface controller for a Virtex-6 FPGA based on the DDR3 interface controller provided by MIG 3.3. The memory interface signals need a 1.2V IOSta...Need support for differential 1.2V IOStandard on Virtex-6
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