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Comp.Arch.FPGA
Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.
There are 17402 threads in our archives.
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CFP with extended deadline of Apr. 10: The 2011 Intl. Conf. on Wireless Networks (ICWN'11), USA, July 18-21, 2011
A. M. G. Solo - 2011-04-06 08:21:00
Dear Colleagues:
Please share the announcement below with those who might be
interested.
Thank you, Organizing Committee
------------
CALL FOR PAPERS
==========...
Ideal FPGA Development Kit [24 articles]
allen - 2011-04-06 06:06:00
Hey guys,
I work in the FPGA development kit sector, and I was just looking to
see if you guys had any ideas regarding what would be your MUST HAVE
features on an FPGA dev kit?
Thanks in advan...Re: SCons build tool as an alternative to makefiles [2 articles]
Eric Anderson - 2011-04-05 07:59:00
On Mon, 20 Aug 2007 13:49:01 +0000, young wrote:
"Patrick Dubois" writes:
> Just to come back on the subject of Scons for a minute... Any input on
> that tool? Or does anyone have another su...MIPI CSI-2 camera interface to parallel [6 articles]
Nico Coesel - 2011-04-05 03:30:00
I've run into a bit of a problem. A camera module I would like to use
has a MIPI CSI-2 interface. The SoC I want to connect to only has a
parallel camera interface. How difficult would it be to us...Virtex 5 PCIe Debug
maxascent - 2011-04-02 06:38:00
I am trying to debug a Virtex 5 PCI Express core. When I insert it into a
PC it is not detecting it. I have chipscope connected to the LTSSM state
machine signals and it seems to be stuck in state 2. ...Doubts about OC PCI Bridge
Sink0 - 2011-04-01 17:56:00
I am trying to make use of OC PCI Bridge, and it is working fine on
the PCI Target side. But when i am trying to master the bus using my
wishbone slave i was having a wrong behavior from the Wb slav...Spartan 3e FPGA and data from matlab workspace. [2 articles]
cavalry - 2011-04-01 02:22:00
Hey,
I need to send data(1158 samples x 21 features) to Spartan 3e FPGA board
from the matlab workspace with rs232 and then do K-means classification on
that and then return the data (1158samples x...MAX II CPLD and I2S Clock divider jitter [5 articles]
Mark - 2011-03-30 15:23:00
I have MAX II CPLD with clock of 24.576 MHz as input coming from the
external crystal oscillator. This clock is used inside the CPLD to
generate sub clocks, thats no problem. Also, my design needs t...MCode Block Problem [2 articles]
mah@k-space.org - 2011-03-30 08:20:00
HELLO
I want to use the below function to the xilinx system generator MCode
Block, but I faced some errors . how to solve this problem.The code
executed well in matlab but when I used MCode Block it ...Xilinx DDR3 controller: rewrite mode registers [3 articles]
Martin Herrmann - 2011-03-30 02:39:00
Hi,
I am using the Xilinx DDR3 controller (MIG). I need to trigger rewriting
the mode registers of the DDR3 component during operation. The
controller does not support this, so I'm working on a m...