Sign in
Search Comp.Arch.FPGA
fpga by Keywords
Altera | ASIC | CPLD | Cyclone | DCM | DDR | DSP | Ethernet | ISE | JTAG | Linux | LVDS | Microblaze | ML310 | Modelsim | NIOS | OPB | PCI | Quartus | RocketIO | SDRAM | Spartan | Spartan3 | SRAM | Stratix | Verilog | VHDL | Virtex | Virtex-4 | Virtex-II | Xilinx | XST
Ads
See Also
Comp.Arch.FPGA
Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.
There are 17402 threads in our archives.
You are looking at page 33 of 1741.
The threads with the newest articles are listed first.
fpga express 3.6 [7 articles]
electrocoder - 2011-03-28 14:32:00
i want "fpga express 3.6" setup program. i have "ftp://ftp.xilinx.com/
pub/swhelp/M3.1i_updates/fpgaexp35.exe" update files. i want setup
program. thanks.
...
Spartan IOB Input Switching Characteristic [3 articles]
Michael - 2011-03-28 13:19:00
Hi,
I have a fully routed Spartan3(Alliance 9,2) that I would like to keep
the routing and only change the "IOB Input Switching Characteristic" for
all used IOs, I know how to do this in the FP...Problems connecting with Xilinx Spartan-6 FPGA [3 articles]
DaMunky89 - 2011-03-27 22:53:00
Currently, when trying to download the bitstream to this SP605 board,
I get the following error:
FPGA configuration encountered errors.
Program FPGA failed
ERROR: Connection to Board Failed
...How to take signals fed to EXT_CLK_P and EXT_CLK_N SMA connectors from a Virtex II Pro board [12 articles]
Pratap - 2011-03-27 20:50:00
Hi,
I want to delay a signal precisely by taking out the signal from the
FPGA so that it can be fed to another chip which can control the delay
through that. I want to feed this delayed signal back...Measuring the delay between two rising edges in modelsim simulation through command/tcl script and writing them to a file. [5 articles]
Pratap - 2011-03-26 09:00:00
Hi,
I want to measure the delay between two rising edges in modelsim
simulation. There are commands in spice like tools where the .measure
statements are used to measure the delays. But I am not ab...Alternative To Altera's Cyclone III Starter Board [5 articles]
Abby Brown - 2011-03-25 14:34:00
Hi,
Does someone produce a cheaper and simpler substitute for
Altera's Cyclone III starter board? It needs to connect to a
laptop to download configuration and test cases and upload
results ...RAM - DIMM vs SO-DIMM: price vs. (hardware & software) ease of use [37 articles]
sdaau - 2011-03-24 11:31:00
Hi all,
I am speculating about starting an FPGA based project soon, which may need
to use RAM. So I'd like to leverage the (relative) abundance (and thus,
hopefully low price) of desktop (or lapto...SRL as a synchroniser [8 articles]
Allan Herriman - 2011-03-24 10:19:00
Hi,
At a client's site I have some legacy VHDL code that is being synthesised
with Xilinx XST 13.1 with Virtex 6 as a target.
This code has some clock domain crossing circuits that use two fli...pcb&bitstream [92 articles]
geobsd - 2011-03-24 10:03:00
hi all
i stupidly bought 5 spartan 3E when i just understoud the power of
fgpa !
so now i need a not expensive fgpa-pcb maker to put the 5 spartan in
my tablet
also i need the bitstream spec to d...Cortex M1 and GUI [2 articles]
RonGr - 2011-03-24 09:53:00
Hi NG.
Have anyone worked with the Cortex M1 Softcore processor and some kind
of graphical user interface?
Does the processor have enough processing power to control such a GUI
(for example on...