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Comp.Arch.FPGA
Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.
There are 17402 threads in our archives.
You are looking at page 34 of 1741.
The threads with the newest articles are listed first.
Xilinx EDK - max array size [3 articles]
Tobias Baumann - 2011-03-23 08:45:00
Hi
I want to handle an array with some hundred elements.
Here is an example code:
#include "xmk.h"
#include "sys/init.h"
#include "platform.h"
#include "xbasic_types.h"
#include
#...
Video Framebuffer using Nexys2 (Spartan-3E) [7 articles]
Ste - 2011-03-23 02:44:00
Hello, I am currently working on a school project that involves interfacing
an external video device with my Nexys2-1200 (XC3S1200E-4FG320) development
board. The device has a resolution of 256x384 w...Via in Hyperlynx linesim [3 articles]
Mark - 2011-03-22 13:31:00
Is there anyway to specify via in HyperLynx LineSim? For example, I
have a transmission line with microstrip of length 20mm on top layer ,
then goes through a via to inner layer for microstrip and a...has already seen over the past few weeks, and have enclosed a press release in couple co
www.jersey-2009.com - 2011-03-22 03:09:00
has already seen over the past few weeks, and have enclosed a press
release in couple couple climbed in the opposite change. Nike Air Max
Now we see the shoes in suede, leather and Flywire build a...Finding cheap PCI-E FPGA board for a student [8 articles]
dormanpeter1@gmail.com - 2011-03-21 16:16:00
Hi,
I am searching for a cheap fpga board (with Altera or Xilinx FPGA)
that has PCI-E or ExpressCard connector (x1 is high enough).
I need just DDR(1/2/3)_SDRAM, GPIO connector, maybe USB-JTAG.
...NIOS II license? [3 articles]
Frank Buss - 2011-03-20 05:23:00
I've developed a NIOS project some years ago for a client and with the
free web edition I could create only encrypted VHDL files with the SOPC
and a time limited SOF file with Quartus, which worked ...Command line for fuse (behavioral sim), for ISE WebPack 9.2/xtclsh? (dbl) [7 articles]
sdaau - 2011-03-19 09:31:00
Hi all,
First, sorry for the double post - it's been a while, and I first tried to
post through fpgacentral.com, forgetting that it does *NOT* apparently
forward the message to usenet:
http://...DMA (memory to memory) [2 articles]
soonph87 - 2011-03-18 12:54:00
Hello, I am having a problem using DMA. When I run my code in Altera DE2
Board, the program stucks at "while (!txrx_done)". It seems like it has
infinite loop. I dont know what happen. Please assist. ...Reg DCM_CLKGEN primitive for Spartan-6 [2 articles]
Aditi - 2011-03-17 22:03:00
Hi all,
I am working on a Spartan-6 FPGA.
I am using a DCM (DCM_CLKGEN Primitive) to generate some clock rates
that I want to.
Here is how I declare the DCM
DCM_CLKGEN g723clk_dcm (...Problems with Xilinx SDK and LwIP [6 articles]
DaMunky89 - 2011-03-17 21:36:00
Alright, so I'm trying to compile the example projects from xapp1026,
following the instructions included in xapp1026.pdf:
www.xilinx.com/support/documentation/application.../xapp1026.pdf
I'm usi...