Sign in
Search Comp.Arch.FPGA
fpga by Keywords
Altera | ASIC | CPLD | Cyclone | DCM | DDR | DSP | Ethernet | ISE | JTAG | Linux | LVDS | Microblaze | ML310 | Modelsim | NIOS | OPB | PCI | Quartus | RocketIO | SDRAM | Spartan | Spartan3 | SRAM | Stratix | Verilog | VHDL | Virtex | Virtex-4 | Virtex-II | Xilinx | XST
Ads
See Also
Comp.Arch.FPGA
Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.
There are 17476 threads in our archives.
You are looking at page 39 of 1748.
The threads with the newest articles are listed first.
Fun with Xilinx Constraints [2 articles]
Rob Gaddi - 2011-04-09 10:49:00
I'm working on a Spartan 3 design and trying to figure out how, if at
all, I can constrain what I'm looking for without resorting to hand
placement and directed routing.
I've got an analog puls...
Little help with OC PCI Bridge (again)
Sink0 - 2011-04-08 18:39:00
Hi, i am trying to ake use of OC Pci Bridge on my designe, and finally
i could make it work as i want. I can master the network and receive/
send bursts of data on Linux. But i need a sugestion now....What are the preferred Virtex5/Virtex6 configuration methods? [4 articles]
Rich - 2011-04-07 15:29:00
Hello all,
In a seperate thread, there was a brief discussion on what features
are needed in a evaluation kit. So related to that, I'm wondering
what is the preferred method out there for config...Develop Software or Systems? Receive Guaranteed $10 or have $10 Donated to FIRST; Chance to Win an iPad 2
OnTargetEmbedded - 2011-04-07 12:59:00
VDC is conducting its annual survey of embedded engineers, and if you
are involved in the engineering of mobile or embedded systems/
software, this is your chance to influence key embedded solution
...Help with SDC (specifically edge_shift) [4 articles]
James - 2011-04-06 17:52:00
I want to use create_generated_clock to generate a clock that is half
the frequency of the source clock and also phase shifted by 90
degrees. I'm using Xilinx's new SDC support which does not have ...RocketIO [2 articles]
Ernest Scheiber - 2011-04-06 10:30:00
Hello all,
I am trying to understand whether it is possible to extract a clock
from the serial stream and use it as reference for the PMA PLL.
According to what I read so far it is not customary,...CFP with extended deadline of Apr. 10: The 2011 Intl. Conf. on Wireless Networks (ICWN'11), USA, July 18-21, 2011
A. M. G. Solo - 2011-04-06 08:21:00
Dear Colleagues:
Please share the announcement below with those who might be
interested.
Thank you, Organizing Committee
------------
CALL FOR PAPERS
==========...Ideal FPGA Development Kit [24 articles]
allen - 2011-04-06 06:06:00
Hey guys,
I work in the FPGA development kit sector, and I was just looking to
see if you guys had any ideas regarding what would be your MUST HAVE
features on an FPGA dev kit?
Thanks in advan...Re: SCons build tool as an alternative to makefiles [2 articles]
Eric Anderson - 2011-04-05 07:59:00
On Mon, 20 Aug 2007 13:49:01 +0000, young wrote:
"Patrick Dubois" writes:
> Just to come back on the subject of Scons for a minute... Any input on
> that tool? Or does anyone have another su...MIPI CSI-2 camera interface to parallel [6 articles]
Nico Coesel - 2011-04-05 03:30:00
I've run into a bit of a problem. A camera module I would like to use
has a MIPI CSI-2 interface. The SoC I want to connect to only has a
parallel camera interface. How difficult would it be to us...