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Comp.Arch.FPGA
Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.
There are 17402 threads in our archives.
You are looking at page 4 of 1741.
The threads with the newest articles are listed first.
opendous-jtag support for independent USB drivers for JTAG/Impact/Chipscope?
wzab - 2012-01-11 11:11:00
Hi,
Probably most Linux users working with Xilinx tools use the excellent
drivers written by Michael Gernoth and available at http://rmdir.de/~michael/xilinx/
I'm looking for a way to embed the...
Beginner question on FIFO in "FPGA prototyping by VHDL examples" [9 articles]
Bill - 2012-01-09 09:23:00
I am very new to FPGA programming. I'm using "FPGA Prototyping by
VHDL examples" to learn VHDL. I've gotten up to section 4.5.3 FIFO
buffer, and am having trouble understanding what might happen i...voltage drop on STRATIX FPGA supply planes [13 articles]
colin_toogood@yahoo.com - 2012-01-09 03:18:00
Guys
I'm doing hyperlynx power integrity analysis on a Stratix 4 0v9 power
plane. It is showing a 30mV voltage drop across the BGA itself, let
alone getting the power to the BGA which is dropping...Handling overflow in a self-repeating frequency counter [11 articles]
Philip Pemberton - 2012-01-07 03:14:00
Hi guys.
I'm currently working on the HDL code for an open-source project which
images 'strange and unusual' magnetic media (mainly floppy discs but also
MFM and RLL hard disc drives).
To do...slimming down ISE install [4 articles]
Mike Harrison - 2012-01-04 09:38:00
Just installed ISE webpack 13.3 on my laptop and things are getting a bit tight space-wise - a lot
of space (several gb) appears to be used by files for device families I'll never use, but removing
...Clock distribution for ADC and jitter [8 articles]
Benjamin Couillard - 2012-01-03 15:18:00
Hi everyone,
I've got a question regarding clocks and jitter. Let's say I have 2
ADCs that need an input clock of 80 MHz. have an 80 MHz low-jitter
crystal connected to an FPGA and then I use the...Verilog module in VHDL project - ISE 13 [2 articles]
Mike Harrison - 2012-01-03 08:35:00
I want to use the Xilinx Spartan-6 XAPP495 HDMI/DVI transmit/receive modules, which are written in
Verilog, in a new VHDL project, as I'm much more familiar with VHDL - I don't do enough FPGA stuff
...DEBUG a FIFO output on Virtex5 using CHIPESCOPE [2 articles]
fanakin - 2012-01-03 08:30:00
Hi All,
I'm a relatively newbe of FPGA development.
We are working on a design involving BFSK modulator / demodulator pair.
We are usign the built-in FIFO18 component of Xilinx for Virtex5.
For so...Regarding FFT & IFFT CORE IN XILINX
varun_agr - 2012-01-03 05:13:00
Sir
I am trying to use FFT 5.0 core in xilinx as follows for 50 hz Sin
WAVE(THROUGH ADC)for noise removal
1. 64 Transform size
2. Radix-2 burst mode
3.I/p data width 8 bit
4.Scaled
5. Natural or...Xilinx platform cable crashes SL6.1 box
General Schvantzkoph - 2011-12-23 16:17:00
Has anyone else experienced systems crashes caused by the Xilinx platform
cable, it's happening to me a couple of times a day.
I'm using SL6.1 (RHEL 6.1 clone) and ISE 13.3. The scenario is that...