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Comp.Arch.FPGA
Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.
There are 16333 threads in our archives.
You are looking at page 4 of 1634.
The threads with the newest articles are listed first.
Help with avoiding ground-loops on my PCB+external [8 articles]
digitaljanitor - 2010-03-02 12:23:00
All,
Apologies for the cross-post, I know a lot of people who deal with
FPGAs are also experts with PCBs, stack-ups, high-speed layout, hoping
for some good ideas from both groups. I'm not an ex...
LVDS i/o in a SystemVerilog Interface block [3 articles]
fpgabuilder - 2010-03-02 11:53:00
I need to instantiate LVDS interfaces in my top-level. I am planning
to use SV interface blocks. Altera's documentation suggests that LVDS
i/os should only be instantiated using a megafunction. B...Frustration with Vendors! [39 articles]
rickman - 2010-03-02 05:21:00
Sometimes vendors act like they don't want you to use their parts. I
am looking for rise/fall time information on an FPGA output in one
voltage mode LVCMOS33 and the various drive and slew rate opt...Need support for differential 1.2V IOStandard on Virtex-6
Shant - 2010-03-01 21:53:00
Hi all,
I'm designing an LPDDR2 SDRAM memory interface controller for a
Virtex-6 FPGA based on the DDR3 interface controller provided by MIG
3.3.
The memory interface signals need a 1.2V IOSta...Derived clock violation in Virtex4 [11 articles]
Verictor - 2010-02-27 19:08:00
Hi,
I have a V4 with input clock frequency running at 130MHz. This clock
goes into a DCM then CLK0 goes out to other logic. The CLK0 net is
named as "derived_clock" by Synplify. Now the timing re...FPGA Editor - Post Route Simulation after changes in Ncd file [3 articles]
Charles - 2010-02-27 12:15:00
Hi All,
I am new to the FPGA design flow. Now I am working on FPGA editor to
make changes in the design. Once I make changes in the ncd file i can have
either a modified ncd file or a bit file...Altera data sheets. [14 articles]
Symon - 2010-02-27 09:22:00
If anyone from Altera reads this forum, can they please email/call their
manual writing & publishing department and complain from me that their
stupid PDF manuals have occasional pages turned at 9...What is the most area efficient CRC method [7 articles]
dlopez - 2010-02-27 09:03:00
Hi,
I need to implement CRC detection in a Spartan3 Xilinx FPGA. My data stream
is coming in one byte at a time, but I do have about 8-10 clock cycles
between each byte (still tbd!).
If I want to...Quartus - How to get a vector waveform file longer than 1000ns? [2 articles]
Giorgos Tzampanakis - 2010-02-26 22:28:00
I have the Web Edition of Quartus and I can't seem to find how to
generate a vector waveform file longer than 1000ns. Is it
possible?
...Drigmorn3 - Spartan-6 Board Update
John Adair - 2010-02-26 13:52:00
If you were all wondering why we have not had stock recently on this
board we took some feedback and then took the opportunity to shoehorn
some more features into this board.
We have improved the...