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Comp.Arch.FPGA
Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.
There are 16714 threads in our archives.
You are looking at page 4 of 1672.
The threads with the newest articles are listed first.
vMAGIC 0.3.9 released
CP - 2010-08-18 07:24:00
Hi folks!
We are proud to announce version 0.3.9 of the vMAGIC libraries with a
number of improvements. Most importantly, this will be the last alpha
release as we want to keep the API stable from ...
How to use VIO and core inserter at the same time. [11 articles]
aaron123 - 2010-08-18 00:50:00
Hi,
I'am seeking a way to use VIO and core inserter at the same time. I
found that if I want to use VIO , I must also instantiating ILA. I feel
it's awkward.
Please help me find a better way.Tha...Spartan3a: improving DCM performance and "To achieve optimal frequency synthesis performance..." warning [7 articles]
Philip Pemberton - 2010-08-17 17:52:00
Hi guys,
Can anyone explain the following INFO alert I saw in my ISE build log?
INFO:PhysDesignRules:772 - To achieve optimal frequency synthesis
performance
with the CLKFX and CLKFX180 ou...Dumb VHDL Question -- Type Conversion [14 articles]
Tim Wescott - 2010-08-17 14:39:00
How do I assign an integer value to 'signed' or 'unsigned' from the IEEE
libraries?
I'm having this difficulty with my test benches. Surely there's a set
of library functions to do it, but I c...I have problem in writing testbench [2 articles]
somayeh2010 - 2010-08-17 09:23:00
This is my testbench code.
When I load it and want see signals in wave, after I add it, wave is
empty.
I do everything but the problem isn't solve.
Can anyone help me?
library ieee;
use ieee.st...CoreTimer programming in Actel SoftConsole
self - 2010-08-13 14:09:00
Hello,
I am trying to measure the execution time of some code using a
CoreTimer block connected to a Cortex-M1 processor design in an Actel
Fusion part.
My problem is that TMR_current_value()...XC5VTX240T-2FF1759I4177 [3 articles]
FPGA - 2010-08-12 22:37:00
Could someone please help me to identify the suffix, "4177", on this
Virtex-5 device and what it calls out as well as the meaning? Could I
use this device in replace of the XC5VTX240T-2FF1759I (With...DMA operation to 64-bits PC platform [23 articles]
Frank van Eijkelenburg - 2010-08-12 14:42:00
Hi,
I have a custom made PCIe board with a Virtex 5 FPGA on which I
implemented a DMA unit which uses the PCIe endpoint block plus v1.14.
I also implemented simple read/write operations from the ...Altera Sales
luudee - 2010-08-12 00:55:00
Does anybody have an email address for Altera Sales in South East
Asia ?
All email to Altera and their distributors is not being answered.
Thanks,
rudi
...Instantiating non-global clock buffers (Xilinx ISE) [8 articles]
Fredxx - 2010-08-11 14:24:00
I have a design with too many global clocks which ISE automatically adds.
Some of these clocks are slow and feed into relatively small areas of logic.
Is there a way I can specify these clocks t...