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Comp.Arch.FPGA
Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.
There are 17476 threads in our archives.
You are looking at page 44 of 1748.
The threads with the newest articles are listed first.
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encryption in FPGA [5 articles]
REDDY PRASAD REDDY - 2011-03-02 15:04:00
my project is implementing of blowfish algorithm in FPGA and sending
the data from PC through FPGA and encrypt the data.for this which
protocols i can use.please tell me some links related to it.
...Signal issues [3 articles]
aleksa - 2011-03-02 14:09:00
I have a PCB with big pads all around the
FPGA (XC3S50A VQFP 100) so I can solder
the wires on the pads and do some testing.
I've done plenty of tests, possibly damaging the chip.
After the last...S3E1600 Digilent drivers [2 articles]
fili - 2011-03-02 02:10:00
Hello
Today I finally got my Spartan 3E 1600 eval board from Digilent. The
problem is that that I can't make it work with the USB cable programmer. I
think it's something wrong with the drivers.
W...Slice Usage [3 articles]
Turj - 2011-03-01 19:04:00
Dear all,
I am using XST 12.1 for sythensis and for the first time I had a look at
how many slices are occupied by my design. I have to say, I am bit
overwhelmed by the results, with Virtex II y...PLL Cyclone III vs PLL(DLL) Spartan-3AN [5 articles]
Eugen_pcad_ru - 2011-03-01 17:17:00
Hello all!
I need pll which can:
1) 40 MHz -> 320 MHz (0 deg),
320 MHz (15 deg),
320 MHz (30 deg),
320 MHz (45 deg),
320 MHz (60 deg)
...xilinx spartan 6 [3 articles]
Serkan - 2011-03-01 14:47:00
I need to route a FAST CLK (that is used for deserializing and input
to only one bank) to another bank's IODELAY2 and IOSERDES2 elements.
Is this possible?
Please remember that I also need to s...Simulation vs. Hardware mismatch [7 articles]
Patrick - 2011-03-01 09:39:00
Hi all,
I have a very simple problem but I do not get my head around what is
going wrong. Essentially, the whole thing works fine when simulating it,
however, having it in hardware gives me the...Question regarding bitstream generation [7 articles]
Richi - 2011-03-01 06:44:00
Hi all,
I have a very simple VHDL module, consisting of a few lines of code.
The thing is, when I generate the bitstream, I end
up with a huge bitstream. The reason for this is, I guess, that XST...regarding usage of IOBs and Warning XST 2036 [6 articles]
Vivek Menon - 2011-02-28 17:33:00
I am implementing a design using Virtex-6 Device:XC6VLX550T Package:FF1759 =
and Speed:-2.
My top module instantiates 16 units, where each unit instantiates 18x8 mult=
iplier 49 times. This means...