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Comp.Arch.FPGA

Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.

There are 17402 threads in our archives.

You are looking at page 5 of 1741.

The threads with the newest articles are listed first.

united governments of planet earth [2 articles]

the universal being - 2011-12-23 12:44:00
United Governments of Planet Earth All human beings are equal creatures regardless of their color, race, religion, or nationality. No majority ethnic group have the right to ...united governments of planet earth

Equivalence between "XtremeDSP48 slice" and "slices of programmable logic" [4 articles]

MN - 2011-12-22 11:47:00
Hi folks! In this page (http://zone.ni.com/reference/en-XX/help/371599F-01/lvfpgaconcepts/dsp48e_top/) I've found this: "Each DSP48E slice (Xilinx Virtex-5) is equivalent to over 500 slices of pro...Equivalence between

High-bandwidth Digital Content (HDCP) keys with FPGA?

Morten Leikvoll - 2011-12-19 07:06:00
Does anyone know how I could safekeep HDCP keys legally by implementing the HDCP (and HDMI/DisplayPort) engine in FPGA? (Yes, I know HDCP is cracked and that I can generate keys using the leaked ...High-bandwidth Digital Content (HDCP) keys with FPGA?

D-Type Flip flop with negated Q in Webise for a schematic capture [16 articles]

Giuseppe Marullo - 2011-12-13 16:14:00
Sorry for the naive question, but how do I capture a schematic with a D and J-K FF that do have negated Q? I tried to draw the schematic with WebISE 13.3 and there is not such a thing readily avai...D-Type Flip flop with negated Q in Webise for a schematic capture

On-chip, high-speed CAN tranceiver in NXP LPC11Cxx [2 articles]

=?ISO-8859-1?Q?Heinz=2DJ=FCrgen?= Oertel - 2011-12-13 11:29:00
Hello, Who knows if the transceiver is really on-chip or if it is two die solution in one housing? Heinz ...On-chip, high-speed CAN tranceiver in NXP LPC11Cxx

Need Clocked 1.5+Ghz LVDS buffer. Or bright ideas! [2 articles]

2011-12-12 06:42:00
HI Folks; I've been asked to design a VITA57 board. I need to loop back all LA and HA signals as 2.5 volt LVDS. My customer has given me the following requirements: Carrier board has 1...Need Clocked 1.5+Ghz LVDS buffer. Or bright ideas!

Lattice buys SiBlue for $62 million [3 articles]

rickman - 2011-12-10 19:52:00
I think this will be one of the more significant semiconductor acquisitions of the year. http://www.fpgagurus.edn.com/blog/fpga-gurus-blog/lattice-picks-siliconblue-62-million I've been using L...Lattice buys SiBlue for $62 million

Horsepower On Tap [8 articles]

Rob Gaddi - 2011-12-09 03:43:00
I was waiting for Quartus to finish crunching my latest build, and poking around idly on NewEgg trying to see what it would cost to get a machine with a little more juice to it. I started thinkin...Horsepower On Tap

Xilinx 7 series PCIe core models vs. Icarus Verilog [7 articles]

Stephen Williams - 2011-12-08 20:33:00
We are looking for simulation models for the Xilinx 7 series FPGA PCIe core. We use Icarus Verilog models extensively, but the models that Xilinx provides are encrypted, so locked in to a small s...Xilinx 7 series PCIe core models vs. Icarus Verilog

DDR2 read interface [2 articles]

Sachin - 2011-12-08 05:28:00
Hello, I have a question regarding DDR2 memory controller. In a read operation from DDR2 based on strobe, do one need to shift the strobe by 90' in order to capture the valid data, or is there any pt...DDR2 read interface
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