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Comp.Arch.FPGA


Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.

There are 16333 threads in our archives.

You are looking at page 5 of 1634.

The threads with the newest articles are listed first.

EDK spi ip core [6 articles]

lakshmi3489 - 2010-02-25 22:46:00
1. If I look at the spartan 3a 3400 dsp evaluation board schematic there is as SPI EEPROM. Looking at the part number it is a part number for a FLASH by Microchip(M25P16-VMW6G). 2. Looking at thi...EDK spi ip core

How a state machine is constructed using latches? [24 articles]

Weng Tianxiang - 2010-02-25 20:01:00
Hi, Sometimes, when an if statement misses a "else" statement part in a two-process method for a state machine, a latch-type state machine would be built. I always wondering how the state machin...How a state machine is constructed using latches?

Xilinx XPS crash on Linux [2 articles]

pes - 2010-02-25 15:00:00
Hi, I want to test Microblaze processor with Xilinx tools. After creating a MicroBlaze project with the Xilinx Platform Studio, the application crashes. Same crash happens when I open this pro...Xilinx XPS crash on Linux

Scrubbing in Virtex-4 [2 articles]

xabi - 2010-02-25 10:12:00
Hi all, Iam experimenting with Scrubbing in Xilinx Virtex-4 devices. According to XAPP1088, pag.18: "For scrubbing operations, there are special considerations for designs utilizing distributed...Scrubbing in Virtex-4

Scrubbing in Virtex-4

xabi - 2010-02-25 07:30:00
Hi all, I am experimenting with Scrubbing in Xilinx Virtex-4 devices. According to XAPP1088, pag.18: "For scrubbing operations, there are special considerations for designs utilizing distribute...Scrubbing in Virtex-4

Xilinx iodelay [2 articles]

Chris Maryan - 2010-02-24 17:41:00
Intuitively, the iodelay found in Xilinx parts should be just a tapped delay line. But the need for a reference clock at a precise frequency indicates otherwise. Does anyone have any insight into ho...Xilinx iodelay

data2mem and rodata/data (Xilinx) [3 articles]

n5ac - 2010-02-24 12:24:00
I have just constructed a bootloader for a Xilinx FPGA. I am trying to get my main application converted to MCS using the flow described in XAPP482 (run data2mem and then xapp482.exe). The issue I'm...data2mem and rodata/data (Xilinx)

timing constraint syntax/fpga editor info [3 articles]

Serkan - 2010-02-24 06:50:00
What is the syntax of this below constraint? I am using xilinx 11.4, spartan 6, and VHDL I have a signal say "a" that goes to 2 different "obufds". The delay between this "a" signal to the pins...timing constraint syntax/fpga editor info

Data2Mem ? BlockRAM ? Init BMM and MEM [11 articles]

de4 - 2010-02-23 15:40:00
Please help me I have really mess in my head with titles above. A have got custom processor that uses RAM which is created from Block RAMs. RAM is generated from CoreGen. I was initilizing BlockRAM'...Data2Mem ? BlockRAM ? Init BMM and MEM

Triming timing constraints from pin ... [3 articles]

Dek - 2010-02-23 09:20:00
Hi all, I'm working on a Virtex5 xc5vlx50 and in my design I need to use some block ram. I generated the core with core generator, but when I implement the design I got this warning during mappin...Triming timing constraints from pin ...
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