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Comp.Arch.FPGA
Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.
There are 16714 threads in our archives.
You are looking at page 5 of 1672.
The threads with the newest articles are listed first.
DMA operation to 64-bits PC platform (continued) [6 articles]
Frank van Eijkelenburg - 2010-08-11 11:48:00
Hi,
I have a custom made PCIe board with a Virtex 5 FPGA on which I
implemented a DMA unit which uses the PCIe endpoint block plus v1.14.
I also implemented simple read/write operations from the ...
Best clock output pin in Spartan-3 [5 articles]
apalopohapa - 2010-08-10 19:32:00
Hello.
I am using a global buffer input as clock input, the signal then goes
through a DCM, and I need to output the inverted clock through a pin into
another chip. Can I use any pin for this cl...VHDL newbie- stuck just weeks before project submission :(..please help [6 articles]
lastminutepanic - 2010-08-10 19:03:00
Hello,
For my Masters project, I'm trying to implement a multiplier, and a
MAC where the outputs are calculated per clock cycle and stored in a
text file which can then be used for further proces...Signal value clears for no reason [VHDL, ISE 10.1] [5 articles]
ColdStart - 2010-08-10 10:39:00
Hello,
Well my code is huge... but the interesting part is.. lets say i have some
10 bit wide signal, and in my logic i clear it when it reaches value 768.
Actually its not just signal, its a D ...Multiple builds with different top-level generic [3 articles]
Neill Arnell - 2010-08-10 09:01:00
Hi,
I'm working on a Xilinx FPGA design (VHDL) that uses a top level
generic, and need to build multiple versions of the FPGA where the
generic is the only thing that changes. The generic is u...A question from a VHDL beginner [5 articles]
alessandro.strazzero@gmail.com - 2010-08-07 10:27:00
Dear everybody,
I'm a beginner in using the VHDL and I'm experiencing some problems
during the testing
phase. I have developped a small VHDL model based on an Altera Cyclone
FPGA and,
using Mod...Generic parameters in Actel Libero SmartDesign Components [2 articles]
Aragorc - 2010-08-06 17:06:00
Hello
I need some help for using Actel Libero IDE.
The SmartDesign fonctionnality enable me to design my code as a block
diagramm.
This is a very convenient way to keep global view of my programm...Vendor Tool Stability [10 articles]
Angela O - 2010-08-06 11:48:00
A project I am considering undertaking would require that an FPGA's
implementation flow (synthesis through bitgen) be routinely run in a
scripted form at customer locations by the end customer, like...xilinx usb cable [2 articles]
chinnathurai - 2010-08-06 06:18:00
which cypress tool is used to read or write the PID,VID in EEPROM in xilinx
usb programmer?
I want to read the PID,VID from xilinx spartan-3E starter kit how can i do
that?
------------...Verification of the SEU estimates
rafayhasan - 2010-08-05 15:14:00
Hello All,
I am writing this to seek your guidance in knowing the possible
methods/procedures to verify the analytical SEU estmiates for an FPGA
designs. To my understanding the way to go about it...