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Comp.Arch.FPGA
Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.
There are 16714 threads in our archives.
You are looking at page 6 of 1672.
The threads with the newest articles are listed first.
Connecting "signed" to "std_logic_vector" ports. [8 articles]
Andrew Feldhaus - 2010-08-05 10:41:00
Hi,
As I understand it, good practice dictates that in a synthesis-targeted
setting, components should use ports of type std_logic or std_logic_vector
only.
Certainly Xilinx's IP generation ...
Xilinx EasyPath Pricing [7 articles]
muhammad_umer - 2010-08-05 09:41:00
Hi, i am working on a project where i am developing my architecture on
Virtex-4 FPGA. My ultimate goal is to port my design to Xilinx EasyPath
FPGA. But i dont have any idea, how xilinx charges for im...Logic implementation probelm [5 articles]
salimbaba - 2010-08-05 09:30:00
Hey i am using ise 9.1i for synthesizing my designs for spartan 3 fpgas. I
am facing a very wierd problem.
My system comprises of 1 xcs400 fpga and an ARM 7 processor. My RTL design
is very modular. ...Spartan 3AN Starter Kit. Sell.
siriokds - 2010-08-05 06:23:00
I'd like to sell my Xiling Spartan 3AN Starter Kit (almost new and full
working). http://www.xilinx.com/products/devkits/HW-SPAR3AN-SK-UNI-G.htm
If anyone interested contact me.
Thank you.
...Xilinx ISE Webpack and Pipeline Optimization [6 articles]
Tim Wescott - 2010-08-03 18:43:00
Here's a naive question, from a sometime FPGA user:
A long time ago, a friend of mine who does _real_ digital design work
was telling me how cool the (then new) Mentor tools were, because you
c...PIT interrupt in Xilinx
embedded - 2010-08-03 08:47:00
Hello,
I am using Virtex 4 FPGA in ML 410 board and ISE 10.1. I want to use PIT
interrupt and want to run a subroutine after every 1 second so as to print
a statement. May I know how to use PIT int...Data-path accuracy in IIR filters? [28 articles]
Pete Fraser - 2010-08-02 17:49:00
I am working on a project where I need to
implement 6-th order Butterworth low-pass
filters in an FPGA. In some the bandwidth is
low relative to the input data rate, whereas
others have higher ban...Modify UCF file generated with MIG [3 articles]
Rice - 2010-08-02 16:20:00
Hallo,
I have just created a driver for a DDR2 working with a Virtex 5 FX30T. I
want to add this driver to a bigger project but I do not know very well how
to modify the constrains file in order to...how to store data in i2c slave [2 articles]
Gladys - 2010-08-02 13:57:00
Hi all,
I'm implementing an i2c core using FPGA to build interface between
DSP and sensors, the objective is to configure the sensors using i2c
bus, FPGA first acts as i2c slave and receives all ...FX12 mini module with EDK 10.1
bhatti - 2010-08-01 00:13:00
Hi every one
I need to implement 100Mb ethernet connection on FX12 mini module for data
transmission only. EDK 10.1 XPS Base System Builder gives me two options
for ethernet connection (using power...