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Comp.Arch.FPGA
Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.
There are 16332 threads in our archives.
You are looking at page 7 of 1634.
The threads with the newest articles are listed first.
Unpredictable design [17 articles]
de4 - 2010-02-20 21:03:00
Hello !
I have a very big problem. I created a simple procesor and on simulation it
works fine, on step mode it works fine but when it is running on full speed
of clock it got crazy... :( It should...
What is the basis on flip-flops replaced by a latch [22 articles]
Weng Tianxiang - 2010-02-18 20:35:00
Hi,
I finally understand the reason when a flip-flops can be replaced by a
latch.
Here is the excerpt from the paper "Atom Processor Core Made FPGA
Synthesizable"
Optimized for a frequency rang...what is incorrect about my usage of array with port entity? [2 articles]
brianwfarmer - 2010-02-17 11:10:00
library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity delay_line_interleaved is
generic(
numtaps : integer := 18;
wordlength_in : integer := 1...Board layout for FPGA [69 articles]
TSMGrizzly - 2010-02-17 01:04:00
Hi guys.. I'm getting ready to start working on my first board layout
with a BGA package (FG456). First will be a prototype for sure.
I was just wondering a few things...
Probably the critical pa...Differential Signaling Buffer [2 articles]
lakshmi3489 - 2010-02-16 05:57:00
Hi
Has anyone made use of the Differential Signaling Buffer ipcore in EDK???
I have read the pdf accompanying the ipcore and managed to add it properly.
But I am confused as how to connect the ...The more you read, the more you are confused: about Intel's a patent [3 articles]
Weng Tianxiang - 2010-02-16 01:11:00
Hi,
Recently I read Intel's a patent "Apparatus and a method for embedding
dynamic state machines in a static environment".
http://www.google.com/patents?hl=en&lr=&vid=USPAT5712826&id=yqIeAAAAEBA...Differential Signaling Buffer
lakshmi3489 - 2010-02-16 00:49:00
Hi
Has anyone made use of the Differential Signaling Buffer ipcore in EDK???
I have read the pdf accompanying the ipcore and managed to add it properly.
But I am confused as how to connect the ...Intel's super-pipeline logic circuit paper is found
Weng Tianxiang - 2010-02-15 18:50:00
Hi,
We talked about Intel's super-pipeline logic a few weeks ago, using
latch to replace flip-flops. Now I found the paper: patent number:
5796282.
http://scholar.google.com/scholar?q=5796282&hl...Recover FPGA Verilog or VHDL source from .SOF file [5 articles]
highwayismyway - 2010-02-15 17:08:00
I realize that this might not be appropriate question for this group,
but considering the level of knowledge I thought I would see if anyone
knows much about recovering lost verilog code from a .sof...optimal no of inputs to be given in a test bench [7 articles]
chaitanyakurmala@gmail.com - 2010-02-15 16:44:00
hi all,
lets say there is a system in which there are N -inputs and 1 -
output. lets say N-100 or 1000 etc.
if we want to test it completely we have to give all 2 power N inputs
and examine th...