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Comp.Arch.FPGA


Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.

There are 16714 threads in our archives.

You are looking at page 8 of 1672.

The threads with the newest articles are listed first.

Embedded Multipliers in Altera Cyclone [5 articles]

daniel.larkin@gmail.com - 2010-07-28 04:56:00
Hi all, In my Cyclone 4 based design I'm getting an embedded multiplier inferred, as expected from the following VHDL: C ...Embedded Multipliers in Altera Cyclone

All Digital PLL [6 articles]

Ehsan - 2010-07-27 21:14:00
Hey Folks, I am trying to implemented an all digital PLL on Xilinx FPGAs. First, I wrote some Matlab code to see the functionality of the PLL. Everything seemed to work fine. Then I quantized the...All Digital PLL

RS-Latch [3 articles]

firefox3107 - 2010-07-27 18:55:00
Hey, I have to implement a RS-Latch. I know that it is not a good design practice but because of limited clocks, I have to use it. Now my concerns are that this latch could go metastable. In my d...RS-Latch

temporal logic folding [3 articles]

twospruces - 2010-07-27 16:37:00
all, I would like some feedback on a new FPGA architecture. Are there any serious configurable logic gurus on this group? If there is interest, I will post links to the 3 published papers that ...temporal logic folding

LPM_MULT issues

Pete Fraser - 2010-07-27 14:11:00
I haven't used Altera tools for ages, but I'm working on a Cyclone 3 design now, so I'm trying to understand them. The design is going to use many 20x20 signed multipliers. I had hoped that the s...LPM_MULT issues

sdram stable clock [4 articles]

chinnathurai - 2010-07-26 17:27:00
1.What is a stable clock? 2.How can i generate using DCM in xilinx? or vhdl? --------------------------------------- Posted through http://www.FPGARelated.com ...sdram stable clock

Performing incremental code coverage with modelsim

Jean-Baptiste - 2010-07-26 11:48:00
Hello, I would like to run several simulations one after another with code coverage on modelsim. This is because I have several testbenches, each one testing a particular aspect of the design. ...Performing incremental code coverage with modelsim

FPGA < -- > Processor timing Violations

Pravin - 2010-07-26 05:32:00
Hi, I'm interfacing Actel FPGA with Freescale Coldfire Processor. This interface is operating @ 75Mhz. FPGA output signal (TA -Transfer acknowledge) and FPGA data out is sampled at rising edge b...FPGA < -- > Processor timing Violations

Altera EDA Netlist Writer [6 articles]

Rob - 2010-07-26 04:57:00
Hi, Using Altera Model-Sim to do a gate level simulation. The .vo file that is produced doesn't seem to be modeling the internal RAM's correctly. In the design they are instantiated as 12bit bu...Altera EDA Netlist Writer

Programming the Actel Smartfusion Eval Kit in Linux [13 articles]

shoonya - 2010-07-25 22:49:00
Hi, I recently got the Actel Smartfusion eval kit. Since I use Linux, I am running the windows Libero IDE under wine. While the application runs fine under wine, I am not able to program the dev...Programming the Actel Smartfusion Eval Kit in Linux
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