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Comp.Arch.FPGA
Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.
There are 16333 threads in our archives.
You are looking at page 8 of 1634.
The threads with the newest articles are listed first.
optimal no of inputs to be given in a test bench [7 articles]
chaitanyakurmala@gmail.com - 2010-02-15 16:44:00
hi all,
lets say there is a system in which there are N -inputs and 1 -
output. lets say N-100 or 1000 etc.
if we want to test it completely we have to give all 2 power N inputs
and examine th...
To get higher clock frequencies at output using propagation delays. [11 articles]
Pallavi - 2010-02-15 16:18:00
Hi,
I'm implementing this project where I've to generate higher output clk
frequencies using DCM module. I have used a counter for delay generator,
for propagation delays(Pls suggest if there is an...Repost on 10 layer stack for 1152 pin BGA. [4 articles]
Nial Stewart - 2010-02-15 15:11:00
After Symon's pleading to re-post, here it is...
> > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > >
I'm about to start the l...VHDL vs Verilog [38 articles]
whygee - 2010-02-15 13:03:00
hi,
recently I read a quote about VHDL vs Verilog,
along the lines of "VHDL is made by SW people who
don't understand HW and vice versa"...
Does anybody know the exact wording and origin ?
...How relevant is the Residue Number System (RNS)? [5 articles]
Guy Eschemann - 2010-02-15 12:52:00
In Uwe Meyer-Baese's Book "Digital Signal Processing with Field
Programmable Gate Arrays", I saw quite a lot of references to the (at
least for me) obscure Residue Number System. I'm wondering how
...Can the Altera USB cable attach to a KVM XP VM? [9 articles]
General Schvantzkoph - 2010-02-15 12:01:00
I have a KVM XP VM running on Fedora 12. I'm trying to run SignalTap on
the VM however I can't get the VM to see the USB cable. Virt-manager sees
the cable and I've attached it to the VM but XP do...28nm FPGAs are coming... [16 articles]
Symon - 2010-02-15 06:51:00
I saw this and thought of C.A.F.
http://www.altera.com/corporate/news_room/releases/2010/products/nr-innovating-at-28-nm.html
Fuck-a-doodle-do, 28 Gbps transceivers. Maybe now we will see who ca...Test Post [4 articles]
Nial Stewart - 2010-02-12 21:04:00
I posted a query about 10 layer PCBs for a new board I'm
doing. I caught a reply by Rickman at home via Google, but
it seems to have disappeared now.
My usenet connection's normally pretty reliab...Why is following Verilog code snipper considered a Latch [6 articles]
Test01 - 2010-02-12 20:06:00
I am not sure why the QuartusII synthesis tool is considering
ReqInFifoDataIn[72] a latch and not a flip-flop? ReqInFifoData[72] is
clearly defined as part of synchronous always block. It is getti...Synplify out of memory [5 articles]
Ben Gelb - 2010-02-12 12:39:00
I have a really large lookup table (members of a finite field) encoded
as a function. This function is only ever invoked with a constant
argument, so it shouldn't actually be synthesized. Altera's s...