Sign in

username:

password:



Not a member?

Search Comp.Arch.FPGA



Search tips

fpga by Keywords

Altera | ASIC | CPLD | Cyclone | DCM | DDR | DSP | Ethernet | ISE | JTAG | Linux | LVDS | Microblaze | ML310 | Modelsim | NIOS | OPB | PCI | Quartus | RocketIO | SDRAM | Spartan | Spartan3 | SRAM | Stratix | Verilog | VHDL | Virtex | Virtex-4 | Virtex-II | Xilinx | XST

Ads

See Also

DSPEmbedded SystemsElectronics

Comp.Arch.FPGA


Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.

There are 16714 threads in our archives.

You are looking at page 9 of 1672.

The threads with the newest articles are listed first.

Weighted Round Robin Arbiter [3 articles]

onkars - 2010-07-24 22:52:00
Hi everyone, Can someone kindly provide any good links/tutorials/articles for implementing weighted round robin (WRR) arbitration? Thank you. --------------------------------------- ...Weighted Round Robin Arbiter

Cortex-M1 in Actel in strait VHDL? [3 articles]

self - 2010-07-24 11:19:00
Hello All, I have a requirement to build a SOC design with two Arm cores along with some standard and custom peripherals. The Actel Cortex-M1 enabled FPGA's appear to be ideal for my application...Cortex-M1 in Actel in strait VHDL?

Using std_ulogic at synthesis level [11 articles]

alessandro.strazzero@gmail.com - 2010-07-24 10:07:00
Dear everybody, in the following piece of code ... if sRxOld /= iRx then if vHIGH > = T_500ns then sBit = T_500n...Using std_ulogic at synthesis level

Is Tier Logic doomed ? :-/ [2 articles]

whygee - 2010-07-24 08:28:00
"another one bytes the dust"... According to Processor Watch - July 22, 2010 (sorry, I have no URL, it was sent to me by email) ================================================ Tears for Tier ...Is Tier Logic doomed ? :-/

Parallel Cable IV under Ubuntu Linux 10.04 [7 articles]

Tim Wescott - 2010-07-24 07:20:00
Is there any way to do this? Is there any way to do this without standing on my head? The last time I used ISE this was a Windows box. But I've evolved into a Higher Life Form*, and now I don...Parallel Cable IV under Ubuntu Linux 10.04

WTB: Xilinx USB JTAG Cable [5 articles]

Tim Wescott - 2010-07-23 13:32:00
According to Avnet, Xilinx is out of their USB JTAG cables for weeks. I need one (see post about Linux, Cables, woe, etc.). Anyone got one? Anyone close to Oregon City, Oregon got one? I'm w...WTB: Xilinx USB JTAG Cable

Spartan 6 MCB arcitecture

Gladys - 2010-07-23 12:01:00
Hi all, I'm new in DDR2, I've read the MIG document UG388 but I don't quite understand, I'm wondering if anyones could explain me about the performance of the MCB's internal write/read FIFO datapat...Spartan 6 MCB arcitecture

Xilinx Plan Ahead question [2 articles]

pes - 2010-07-22 11:45:00
Hi, I' m new to Plan Ahead 12.1 and I' ve some values of I/O Ports in red color. It concerns DDR3 pins and values in red are Drive Strength (12*) and Slew Type (SLOW*). What could be the sign...Xilinx Plan Ahead question

How to create a LVPECL_25 output pair (Spartan3, ISE 9.1) [3 articles]

Thomas Heller - 2010-07-22 02:48:00
I'm trying to create a LVPECL_25 differential output on a Spartan 3 (XC3S200 device in PQ208 package). I did this by selecting 'LVPECL_25' in the I/O Standard column in PACE (assign package pins). ...How to create a LVPECL_25 output pair (Spartan3, ISE 9.1)

Xilinx' partition flow in ISE12.1 [2 articles]

Sean Durkin - 2010-07-20 14:00:00
Hi *, has anyone had any success with the "new" partion flow in ISE12.1? I've been fiddling around with this for a few hours, but whatever I try, the design fails to even finish routing on the ...Xilinx' partition flow in ISE12.1
previous | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | next