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Comp.Arch.FPGA
Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.
There are 16332 threads in our archives.
You are looking at page 9 of 1634.
The threads with the newest articles are listed first.
QDRII on StratixIII pinout strangeness
Morten Leikvoll - 2010-02-12 05:19:00
Using QDRII x18 in 2-burst mode, I assume that the data/adr/cmd bus are all
DDR signals using the same clock domain (except the read and write signal
wich are single data rate)
The docs say th...
DONE_cycle:6 setting neccessary in bitgen [18 articles]
Sean Durkin - 2010-02-11 21:50:00
Hi *,
I recently designed a board with a Virtex 5 on it, which I got back from
the assembly line a few days ago. This is not the first board I've
designed, and I've used many FPGA-boards from oth...Multple architectures in ISE top level module? [6 articles]
MikeWhy - 2010-02-11 11:58:00
The top level module in Xilinx ISE 11.1 projects apparently cannot contain
more than one VHDL architecture. If that module is already the top level in
the project, both (all) architectures are mar...Call for Paper The International Journal of Computer Science (IJCS)
editor ijcs - 2010-02-11 00:10:00
Call for Paper
The International Journal of Computer Science (IJCS) publishes
original papers on all subjects relevant to computer science,
communication network, and information systems. The highe...Spartan-3E Starter Kit reconfiguration problems [3 articles]
Uwe Bonnes - 2010-02-10 05:54:00
Hello,
to talk to the SPI flash on the s3e starter kit board, I have some code that
invokes the BSCAN_SPARTAN3 primitive and additional sets and locates
DAC_CS = AMP_CS = SF_CE0 = FPGA_INIT_B = 1...Stratix FPGA board up for grabs for cheap.
Alexander - 2010-02-09 21:48:00
Hello!
Sorry to spam, but this is for a very limited audience. I just placed
my crazy expensive Stratix FPGA development board on E-Bay for cheap
if anyone is interested.
Ebay Item: 2004379295...Spartan-3E Starter Kit reconfiguration problems
Uwe Bonnes - 2010-02-09 14:07:00
Hello,
to talk to the SPI flash on the s3e starter kit board, I have some code that
invokes the BSCAN_SPARTAN3 primitive and additional sets and locates
DAC_CS = AMP_CS = SF_CE0 = FPGA_INIT_B = 1...Xilinx ISE 11.1 crash - Visual Studio error [5 articles]
Daku - 2010-02-09 12:29:00
Could some Xilinx ISE guru provide some hints for my problem ? I am
trying to synthesize a simple 4K RAM block with Xilinx ISE. About half-
way through execution, I get an error message, inside a Vi...SoC benchmarks
Vivek Menon - 2010-02-09 12:00:00
I am looking for SoC benchmarks such as VOPD, FFT, MPEG4 for
performance evaluation on FPGAs.
...Running BMD design on a 64 bit machine
Usama - 2010-02-09 08:26:00
Hi,
i have implemented a BMD design using xapp1052. it is running
successfully on a 32 bit machine. but when i run it on a 64 bit
machine i am facing a problem
the problem is that when i set ...