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Comp.Arch.FPGA
Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.
There are 17402 threads in our archives.
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The threads with the newest articles are listed first.
Xilinx Artix-7 availability [2 articles]
Arne Pagel - 2012-02-04 08:24:00
did anybody hear something about the availability about the Xilinx Artix-7 series?
Especially I am interested in the XC7A8 or XC7A15 in the FTG256 Package.
regards
Arne
...
Design Notation VHDL or Verilog? [27 articles]
vsh - 2012-02-03 09:18:00
any comments on either VHDL or Verilog?
...Difference between Xilinx isim and modelsim [5 articles]
guenter - 2012-02-02 19:48:00
Is it allowed to pass a member of a std_logic_vector to the rising_edge
function?
When doing this, isim doen's detect all changes, while modelsim does.
The code below toggles bits of a 3-bit vector....Virtex6HXT PCIe doesn't come up to Gen2 on Sandy Bridge systems
General Schvantzkoph - 2012-02-02 13:53:00
I have an 8X PCIe core in a Virtex6HXT (version 2.5, the latest in 13.4).
It's configured for Gen2 but it's coming up Gen1. lspci -vvv reports that
both the core and the board are Gen2 capable. I'...=?ISO-8859-1?Q?Post=2Dsynth=E8se_simulation?= [6 articles]
molka - 2012-02-01 10:13:00
Hello,
I want to run a post-synthesis simulation. I don't find where to
choose the sources (Netlist post-synthesis) to launch the needed
simulation from ISE 13.3.
Does someone know how to do i...regarding tft controller
vlsi330 - 2012-02-01 10:12:00
hi,
can you please tell me how to add xps_tft controller ip core in xilinx edk
for spartan 3e fpga board platform?
---------------------------------------
Posted throug...Relative paths in EDK user repository TCL script [4 articles]
kekely - 2012-02-01 04:58:00
Hi,
I'm trying to create EDK repository with my own pcores. In one of this
pcores I need to use special program to generate one of its VHDL source
files. So during synthesis I need to execute some...Active-HDL/Xilinx Core FIFO Gen Sim Problem [3 articles]
roleohibachi - 2012-01-31 10:40:00
Hi there,
I'm using Xilinx 10.1(nt) K.31, and Aldec Active-HDL 8.1 (student). I
used Aldec's design flow tools to implement a Coregen FIFO, and am
using a recent, manufacturer-compiled version of X...TCP/IP [3 articles]
david - 2012-01-31 03:18:00
Hello somebody Know how to link matlab with any device with tcp/ip
comunication
Iam david.
...Open source cable server for Xilinx - for remote running of tools like Chipscope with unsopported target [4 articles]
wzab - 2012-01-30 02:27:00
Hi,
II'd like to know if there exists an open source implementation of
Xilinx cable server, allowing to run it on a platform for which Xilinx
does not provide binaries.
Of course it is possibl...