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Recent Blogs on FPGARelated

Point of View
posted by Christopher Felton

Spline interpolation
posted by Markus Nentwig

BGA and QFP at Home 1 - A Practical Guide.
posted by Victor Yurkovsky

Introducing the VPCIe framework
posted by Fabien Le Mentec

How FPGAs work, and why you'll buy one
posted by Yossi Kreinin

Learning VHDL - Basics
posted by Enrico Garante

Yet another PWM
posted by Anton Babushkin

See Also

DSPEmbedded Systems

Comp.Arch.FPGA interface on FPGARelated

Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.

There are 17906 threads in our archives.

You are looking at page 1 of 1791.

The threads with the newest articles are listed first.

USB PHY recommendations [3 replies]

Posted by Mike Perkins - 12 hours ago

I have started using the TI TUSB1210 which is a USB PHY with a ULPI interface. However, I can virtually guarantee that during enumeration, the device will lock up with DIR permanently DIR hig...USB PHY recommendations

[cross-post] verification vs design [7 replies]

Posted by alb - 17 hours ago

Hi everyone, I've recently had to argue why it is not 'sane' to budget 500 hours of development against 200 of verification. If you ask the FPGA developer he'd say a factor of 2/3 has to be ...[cross-post] verification vs design

Altera 100-pins chip [2 replies]

Posted by Rego - 18 hours ago

Hello, I'm looking for suggestions for an Altera 100-pins chip which I can use in a board like this 100-pins chip

Non-project mode Vivado simulation? [4 replies]

Started by Unknown 1 day ago

Is it possible to run a Vivado simulation in non-project mode? I can't seem to find any documentation on how to do it. ug835 describes which Tcl commands are used for simulation, but not whic...Non-project mode Vivado simulation?

Fast and slow clocks [10 replies]

Started by Unknown 4 days ago

I'm wondering what the correct way to handle the following situation is. Sorry this is a bit long winded. BTW, it's not homework, all that was 40+ years ago. I have two clocks, clk which is the...Fast and slow clocks

Need ideas for FYP [25 replies]

Started by Unknown 4 days ago

I am student of Bachelors and going to start my FYP in some days. I am going into the field of high computation in verilog. These are some projects which I might be doing: 1.the n-body gravitational ...Need ideas for FYP

looking for systemC/TLM 2.0 courses [15 replies]

Posted by alb - 6 days ago

Hi everyone, I apologize if this is maybe not the best audience for these kind of enquiries but I'll try anyhow. I'm looking for a good SystemC/TLM 2.0 training course which is not too basic...looking for systemC/TLM 2.0 courses

Handel-C to VHDL [1 replies]

Posted by Ahmed Ablak - 6 days ago

When I generate VHDL from Handel-C. I always end up with an empty VHDL file, did any one face this problem? and how to solve it? Thanks ...Handel-C to VHDL

ISE 14.6 and picoblaze synthesis problem (translate_on/off directives ignored ?) [5 replies]

Posted by - 1 week ago

Hello I am trying to implement a design containing a picoBlaze (source code I hav= e already used numerous times) in a new project with ISE 14.6, and synthesi= s chokes on the numerous INIT paramet...ISE 14.6 and picoblaze synthesis problem (translate_on/off directives ignored ?)

PicoBlaze IDE

Posted by Erik Chalupa - 1 week ago

Hello, we have developed IDE for Xilinx's softcore processor PicoBlaze with features like macro assembler, simulator and other various tools. Noncommercial license is free of charge. We'll be glad...PicoBlaze IDE

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