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I don’t often convert VHDL to Verilog but when I do ...
posted by Christopher Felton


Spline interpolation
posted by Markus Nentwig


BGA and QFP at Home 1 - A Practical Guide.
posted by Victor Yurkovsky


Introducing the VPCIe framework
posted by Fabien Le Mentec


How FPGAs work, and why you'll buy one
posted by Yossi Kreinin


Learning VHDL - Basics
posted by Enrico Garante




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Comp.Arch.FPGA interface on FPGARelated

Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.

There are 17946 threads in our archives.

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Transfering image file to DDR RAM using EDK [1 replies]

Posted by rashmic - 2 days ago

Hi, I am working on Xilinx Spartan 3e Starter kit board which has DDR Ram. I have to transfer image file to DDR and store it for further manipulation using EDK.Please provide different techniques t...Transfering image file to DDR RAM using EDK

Send a pulse across clocks [14 replies]

Posted by Leo - 2 days ago

Hello, I want to send a pulse from one clock domain to another, knowing tha= t from the time event that this pulse is generated in the source clock doma= in it arrives in the first rising edge of th...Send a pulse across clocks

Where in ISE/Vivado are the chip specific resources listed? [1 replies]

Posted by Svenn - 2 days ago

Hi, I am trying to create a comparison list between various FPGAs in the Xilinx universe. The unisim library lists all primitives, but not all of the primitives listed in unisim are available in ...Where in ISE/Vivado are the chip specific resources listed?

Vivado is intensely frustrating [3 replies]

Posted by Rob Gaddi - 3 days ago

So, the following ROM initialization code should be entirely synthesizable. Not so, according to the latest version of Vivado, which proudly declares "ignoring unsynthesizable construct: non-...Vivado is intensely frustrating

Artix-7 tools, ISE vs Vivado [4 replies]

Posted by Vladimir Ivanov - 4 days ago

Hello, What are the practical pros and cons of using each of ISE or Vivado for the Artix-7 family? I am interested in the basic synthesis/map/routing/STA steps. Aside from possible speed i...Artix-7 tools, ISE vs Vivado

Xilinx XST and initializing block RAMs [10 replies]

Posted by Christopher Head - 4 days ago [ Spartan | Spartan3 | Xilinx | XST ]

Hi all, I'm using XST 14.2 and trying to use block RAMs to store constant data (i.e. as ROMs) for program code that will be run by a CPU. I want to infer the block RAMs during synthesis and then ac...Xilinx XST and initializing block RAMs

Instantiating Components or Using Generate statements

Posted by Abdulla873 - 4 days ago

Hi Guys, Are there any differences between instantiating components and using generate statement in hierarchical structure design?? Thanks, Abdullah --------------------------...Instantiating Components or Using Generate statements

Why two hold checks done byTimeQuest

Posted by kaz - 4 days ago

Hi, TimeQuest says it uses two hold checks per each setup check. The first hold check for previous latch edge with current launch edge and second check for current latch edge with next launch e...Why two hold checks done byTimeQuest

[RANT] XILINX, Are you freaking kidding me ? [8 replies]

Posted by Simon - 1 week ago

So I wanted to know if it was possible to update an old embedded-developmen= t kit license that's expired. There's nothing on xilinx' site as far as I c= an see that allows for old licenses to be ...[RANT] XILINX, Are you freaking kidding me ?

Altera Cyclone II [8 replies]

Posted by Michael - 2 weeks ago

Hi, I have a Altera Cyclone II design where I am looking for a good way to make a complete reset via HDL. In Xilinx there is a STARTUP macro that can be used for reset, does the Altera also ...Altera Cyclone II

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