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Point of View
posted by Christopher Felton

Spline interpolation
posted by Markus Nentwig

BGA and QFP at Home 1 - A Practical Guide.
posted by Victor Yurkovsky

Introducing the VPCIe framework
posted by Fabien Le Mentec

How FPGAs work, and why you'll buy one
posted by Yossi Kreinin

Learning VHDL - Basics
posted by Enrico Garante

Yet another PWM
posted by Anton Babushkin

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DSPEmbedded Systems

Comp.Arch.FPGA interface on FPGARelated

Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.

There are 17888 threads in our archives.

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Free VHDL or Verilog Simulator [8 replies]

Posted by Abby Brown - 3 days ago [ Quartus | Verilog | VHDL ]

Hi, Altera's Quartus II does not include a free simulator. Is there a free VHDL or Verilog simulator that is reasonalbly good? Google shows a few but I would prefer a recommendation. Thanks...Free VHDL or Verilog Simulator

Good VHDL reference? [7 replies]

Started by Nico Coesel 3 days ago [ ASIC | VHDL ]

It seems I have misplaced my VHDL book a long time ago and I can't figure out where I left it. In short: I need a new VHDL book :-( Can anyone recommend a good generic VHDL reference? I'm not look...Good VHDL reference?

VHDL comments in Vim? [5 replies]

Started by Peter Sommerfeld 3 days ago [ VHDL ]

Hi folks, I'm getting tired of commenting large blocks of VHDL code by hand. Anyone know of any Vim scripts that can comment/un-comment a VHDL block? A cursory Google search brings up either...VHDL comments in Vim?

Getting started VHDL, VHDL for Dummies, Easy Steps for FPGA experiments [5 replies]

Posted by Kutaj Vamor - 3 days ago [ Linux | VHDL ]

Dear FPGA and VHDL Experts, I am new to FPGA and VHDL. I would like to learn VHDL and start experimenting FPGA. I beleive I learn faster and better by experimenting. What would you recommend for...Getting started VHDL, VHDL for Dummies, Easy Steps for FPGA experiments

VHDL gate level from Xilinx XST [1 replies]

Started by Laurent Gauch 3 days ago [ PCI | VHDL | Xilinx | XST ]

Hi all, I need to generate a part of my VHDL project as a VHDL gate level IP, in the goal to protect my generic IP core. In fact, I want to protect my own PCI core before delivering the comple...VHDL gate level from Xilinx XST

Know any good public FPGA projects to contribute to? [22 replies]

Posted by signaltap - 3 days ago

Hi all, Can you suggest any good FPGA projects I could contribute to? I have some = free time and want to work on something challenging and interesting. Inste= ad of starting something myself I...Know any good public FPGA projects to contribute to?

Easy PC software tool - Bad experience [12 replies]

Started by Roger 2 weeks ago

Due to a bug in the Easy PC software tool from Numberone Systems, I've just had a very time consuming and costly incident. Despite their faulty software costing me a lot of money, the company have...Easy PC software tool - Bad experience

Functional safety guidelines [2 replies]

Started by Unknown 2 weeks ago

Hello, I wonder maybe someone have automotive functional safety guidelines for VHDL and is willing to share? I think there's a package available from Altera, however they charge 10k for it telli...Functional safety guidelines

xc3sprog: SPI flash access for Spartan 6 LX 25 TFQ256 (Xess Xula 2)

Posted by mnentwig - 3 weeks ago

Hi, I wasn't able to find a bscan .bit file to program the flash on my Xula2 board so I built it myself. Link follows, includes also the .ucf file (only LOCs for the flash pins, nothing else). ...xc3sprog: SPI flash access for Spartan 6 LX 25 TFQ256 (Xess Xula 2)

wrong waveforms in vivado waveform viewer [1 replies]

Started by Unknown 3 weeks ago

Has anyone experience the Vivado waveform viewer just making up waveforms? I have a module with two different signals, lets say x and y if I go down the hierarchy and add them to the waveform v...wrong waveforms in vivado waveform viewer

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