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Recent Blogs on FPGARelated

Spline interpolation
posted by Markus Nentwig

[Comments] C HLS Benefits
posted by Christopher Felton

BGA and QFP at Home 1 - A Practical Guide.
posted by Victor Yurkovsky

Introducing the VPCIe framework
posted by Fabien Le Mentec

How FPGAs work, and why you'll buy one
posted by Yossi Kreinin

Learning VHDL - Basics
posted by Enrico Garante

Yet another PWM
posted by Anton Babushkin

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DSPEmbedded Systems

Comp.Arch.FPGA interface on FPGARelated

Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.

There are 17884 threads in our archives.

You are looking at page 1 of 1789.

The threads with the newest articles are listed first.

xc3sprog "instruction capture is 0x3f" (solved) [2 replies]

Posted by mnentwig - 4 hours ago

Hi, if anybody else runs into the same problem with an FPGA module: xc3sprog failed to upload the bitstream to a Spartan 6 LX45, complaining "instruction capture is 0x3f". The JTAG c...xc3sprog "instruction capture is 0x3f" (solved)

calculations of logic vectors and constant [2 replies]

Posted by itay - 2 days ago

what is the prefered option of arithmetic operations using logic vectors and constant? convert logic vector to integer and do the operation or to convert the constant to logic vector? I have sam...calculations of logic vectors and constant

ZPU-based SoC for Numato Saturn board with DRAM

Posted by mnentwig - 5 days ago

Hi, this is a "public backup" of a holiday project maybe it's of use to someone: - "medium" ZP...ZPU-based SoC for Numato Saturn board with DRAM

LVDS problem - Black magic anyone? [13 replies]

Started by Unknown 6 days ago

I have an LVDS related issue that drives me crazy: There are two boards with a FPGA that are connected by a ca. 30cm cable. On= ly 6 wirea are used: GND + Power LVDS (with embedded clock), 720Mb...LVDS problem - Black magic anyone?

Has anyone forked any Xilinx IP? [4 replies]

Posted by SP - 1 week ago

What is the "recommended" way to do IP forking from Xilinx's repos? Not for public distribution but to have a modified one for specific purposes. The modifications are beyond the customisa...Has anyone forked any Xilinx IP?

Basic question: sequence of execution within FPGAs [10 replies]

Started by Unknown 1 week ago

Trying to get my head around FPGAs after 40 years of 2GLs. I can't seem to find a clear exposition of the following, would appreciate if someone could confirm or clarify the following assumption: ...Basic question: sequence of execution within FPGAs

Professional VHDL Examples? [8 replies]

Started by Unknown 1 week ago

Over the years I have taught myself Verilog and VHDL, and although I am qui= te comfortable with Verilog, I feel as though my VHDL designs are just not = as tight as they should be. In pursuit of s...Professional VHDL Examples?

strange effect with tristate output [4 replies]

Posted by Frank Buss - 2 weeks ago

I'm using a XC95144XL, two pins are an input for a 5V signal, which have pullup resistors (3k3). Setting the pins to low from my VHDL design works great. Then I thought I could set it to high, too, ...strange effect with tristate output

What is the content of "High-speed SERDES interfacing such as PCIe, SDI, SGMII, XAUI" [1 replies]

Posted by fl - 2 weeks ago

Hi, I read a job post which requires: High-speed SERDES interfacing such as PCIe, SDI, SGMII, XAUI I know FPGA vendors have PCIe IP interfaces. What is the job content with the above statem...What is the content of "High-speed SERDES interfacing such as PCIe, SDI, SGMII, XAUI"

multicycle path - synplify pro [2 replies]

Posted by alb - 2 weeks ago

Hi everyone, I'm experiencing an issue with Synplify Pro E-2010.09A-1. I have to insert some multicycle paths in order to be able to implement the design (no option to break the paths with regi...multicycle path - synplify pro

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