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Recent Blogs on FPGARelated

Point of View
posted by Christopher Felton

Spline interpolation
posted by Markus Nentwig

BGA and QFP at Home 1 - A Practical Guide.
posted by Victor Yurkovsky

Introducing the VPCIe framework
posted by Fabien Le Mentec

How FPGAs work, and why you'll buy one
posted by Yossi Kreinin

Learning VHDL - Basics
posted by Enrico Garante

Yet another PWM
posted by Anton Babushkin

See Also

DSPEmbedded Systems

Comp.Arch.FPGA interface on FPGARelated

Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.

There are 17929 threads in our archives.

You are looking at page 1 of 1793.

The threads with the newest articles are listed first.

MIPI M-PHY and FPGA? [6 replies]

Posted by mnentwig - 1 day ago

Hi, does anybody know whether it is possible (or impossible) to use an FPGA's serial transceivers for a MIPI type 2 M-PHY link (i.e. 1.5 GBit/s)? Xlinx' book M-PHY and FPGA?

VHDL Synchronization- two stage FF on all inputs? [38 replies]

Posted by hvo - 3 days ago

Hello, I know this topic is beaten to death but I am a bit unlcear some things. I've recently encountered metastability issues that caused my FPGA to do unpredictable things. Someone suggested ...VHDL Synchronization- two stage FF on all inputs?

Monitor connections [7 replies]

Posted by Rick C. Hodgin - 3 days ago

Is there a way to monitor signals in existing wires? For example, with an oscilloscope and probe I can watch voltage changes. Is there a standard way to connect to an existing, working device, and...Monitor connections

Using FPGA to feed 80386 [85 replies]

Posted by Rick C. Hodgin - 4 days ago

Would it be possible to connect an FPGA up to an 80386 (or other) CPU, to respond to memory and port requests, and leverage it as a resource? I'm thinking software runs on the 80386, given it by...Using FPGA to feed 80386

Which Altera to buy? [68 replies]

Started by Unknown 1 week ago

Greetings. I am new to FPGA programming. I am seeking to create a 40-bit 80386-like CPU core with a 32-bit and 64-bit FPU with 16 registers, a 128-bit four- and two-way 32-bit and 64-bit vector FP...Which Altera to buy?

Problems with Xilinx SDK and LwIP [7 replies]

Posted by DaMunky89 - 2 weeks ago [ Microblaze | Xilinx ]

Alright, so I'm trying to compile the example projects from xapp1026, following the instructions included in xapp1026.pdf: I'm usi...Problems with Xilinx SDK and LwIP

ICE40 Logic Cells [2 replies]

Posted by rickman - 2 weeks ago

I was aware that the ICE40 devices have some limitations compared to other devices that are not so cost and power constrained. Until now the apparent lack of LUT RAM escaped me. I guess it is on...ICE40 Logic Cells

FPGA on Android

Posted by Tim - 3 weeks ago

- non-volatile FPGA plus FTDI USB chip - connects to an Android host mode USB port - application software in Lua, with Java interface/driver - high-level Gideros software for whizzy graphics - FPG...FPGA on Android

Low-end FPGA mezzanine standard [17 replies]

Posted by Theo Markettos - 3 weeks ago

Anyone know if there's a standard(ish) for simple mezzanine cards for FPGA boards? I know about things like FMC and HSMC which are very 'high end' - multi gigabit transceivers, expensive connecto...Low-end FPGA mezzanine standard

Bypass Xilinx flexlm license check [24 replies]

Started by Unknown 3 weeks ago

Hello, While I certainly do not condone piracy, and I believe Xilinx should be com= pensated for their hard work, sometimes it can be handy to run ISE without = limitations on the range of target...Bypass Xilinx flexlm license check

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