Sign in

Not a member? | Forgot your Password?

Search Comp.Arch.FPGA



Search tips

Recent Blogs on FPGARelated

[Comments] C HLS Benefits
posted by Christopher Felton


Signed serial-/parallel multiplication
posted by Markus Nentwig


BGA and QFP at Home 1 - A Practical Guide.
posted by Victor Yurkovsky


Introducing the VPCIe framework
posted by fabien le mentec


How FPGAs work, and why you'll buy one
posted by Yossi Kreinin


Learning VHDL - Basics
posted by Enrico Garante


Yet another PWM
posted by Anton Babushkin




See Also

DSPEmbedded Systems

Comp.Arch.FPGA interface on FPGARelated

Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.

There are 17818 threads in our archives.

You are looking at page 1 of 1782.

The threads with the newest articles are listed first.

JTAG issues Cyclone V SoC [3 replies]

Posted by Al Clark - 1 day ago

I am designing my own Altera Cyclone V SoM board. It is not intended to be a dev board. It will be a function module that also includes Analog Devices' SHARC DSPs. I am working on the JTAG con...JTAG issues Cyclone V SoC

more than 58'000 false paths... [10 replies]

Posted by alb - 2 days ago

Hi everyone, I started adding false paths to my design (see this thread for a context: ) but in order to avoid funny names, I started to add wildcards. My false path constraints look like ...more than 58'000 false paths...

Recovering verilog source file from build files.. possible?

Started by Unknown 3 days ago

My .v Verilog source files were in a separate folder to the IDE build directory, containing all the stuff generated in the build. Then I had a hard disk crash, and (long story) everything *except* t...Recovering verilog source file from build files.. possible?

Cheap spec an using an RTL-SDR

Posted by Les Cargill - 6 days ago

http://hansvi.be/wordpress/?p=91 -- Les Cargill ...Cheap spec an using an RTL-SDR

Spartan 3 JTAG problems [2 replies]

Posted by Mike Perkins - 6 days ago

Has anyone come across an issue where an XC3S200 is recognised in Impact; "Right Click to Add Device or Initialize JTAG chain", and then can't read the device ID, status or indeed do any...Spartan 3 JTAG problems

ERROR:HDLCompilers:27 - "ipcore_dir/Cordic_atan_synth.v" line 61 Illegal redeclaration of 'Cordic_atan' [1 replies]

Posted by Raviraj Makwana - 6 days ago

unable to solve this error.I tried all the thing and check that there is no duplicate module..still its giving error..any one can help???plz ...ERROR:HDLCompilers:27 - "ipcore_dir/Cordic_atan_synth.v" line 61 Illegal redeclaration of 'Cordic_atan'

New Lattice FPGAs on 40nm ? [7 replies]

Posted by Brane2 - 6 days ago

I'm playing with Lattice's MachXO2 and ECP3 for a few months now and now that MachXO3 is about to come out I wonder what happened to ECP4. As I understand it, Lattice found its market niche in low-...New Lattice FPGAs on 40nm ?

Help: Altera megafunctions, Quartus II [3 replies]

Posted by Bruce Varley - 1 week ago

I'm an FPGA newbie, working with the freeware Altera Quartus II IDE. I used the megafunction builder to create a FIFO memory, the .v file it generated is similar to the virtual prototypes created ...Help: Altera megafunctions, Quartus II

Nexys 4 FPGA Board

Posted by marwen brikcha - 1 week ago

Hi all I'm usinf Digilent Nexys 4 FPGA BOard and I won't to run LInux kernel on microblaze and I don't have a lot of information to complete this project . Can anyone help me (link,tutoriel, hel...Nexys 4 FPGA Board

how to specify which feature for a license

Posted by alb - 1 week ago

Hi everyone, we have a license server that hosts both ACTEL_SUMMIT feature (1 seat) and ACTEL_VISTA one (10 seats). Is there a way in Designer to specify either from the command line or thro...how to specify which feature for a license

| 1 | | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 |