Sign in
Search Comp.Arch.FPGA
fpga by Keywords
Altera | ASIC | CPLD | Cyclone | DCM | DDR | DSP | Ethernet | ISE | JTAG | Linux | LVDS | Microblaze | ML310 | Modelsim | NIOS | OPB | PCI | Quartus | RocketIO | SDRAM | Spartan | Spartan3 | SRAM | Stratix | Verilog | VHDL | Virtex | Virtex-4 | Virtex-II | Xilinx | XST
Ads
See Also
Comp.Arch.FPGA
Comp.Arch.Embedded is a worldwide Usenet news group that is used to discuss various aspects of Embedded Systems development.
There are 15675 threads in our archives.
You are looking at page 1 of 1568.
The threads with the newest articles are listed first.
how to use ram or memory [14 articles]
The Lord of War - 2009-07-04 16:08:00
hi all i'm new to the fpga field
i was wondering how do i use the onboard sram, i need to create a big
memory structure so do i just do:
type dataout is array (0 to 1048576) of std_logic_vector(...
50 000 registered users at OpenCores.org [11 articles]
OC-team - 2009-07-04 12:56:00
OpenCores continues to grow rapidly and we are pleased to announce
that we have just passed 50,000 registered users. We have also noticed
a large increase in activity on the site, in both downloadin...Active-HDL simulator recompile... or not recompiling [7 articles]
rickman - 2009-07-04 08:13:00
I have been using Active-HDL (AHDL) for over a year now and I am
pretty happy with it. For one thing, it doesn't have the apparently
unfix-able, tool crashing, memory leak that every version of Mod...Math Integral operation in FPGA [9 articles]
Simon - 2009-07-04 07:43:00
Hi, guys,
I have been several years experience on FPGA networking application
design, but I come up with the a question about math operation in
FPGA. I need to perform Integral operation. I don't...XILINX: verilog is not supported as a language, using usenglish [3 articles]
luudee - 2009-07-04 01:00:00
This should probably go in to the funny error messages folder:
=============== (running make bits within xps) ===============
ChipScope Core Generator command: coregen -b
/home/rudi/reference_d...FPGA / CPLD Group on LinkedIn -- Networking Group [9 articles]
cpld-fpga-asic - 2009-07-03 18:45:00
Group for People Involved In the Design and Verification of FPGA's,
other Programmable Logic , and CPLD's to Exchange Idea's and
Techniques. You should have FPGA / CPLD Design / Verification on your...Cheapest FPGA with decent PCI- e interface ? [10 articles]
Brane2 - 2009-07-03 15:13:00
So far, I have only been able to find Spartan6 ( which isn't really
available yet) from Xilinx and some small FPGA from Actel ( Igloo
family ?).
Trouble is, Spartan has only two lanes, which is ...How to keep documentation of control and status registers and VHDL code in sync [6 articles]
Svenn Are Bjerkem - 2009-07-03 13:23:00
Hi,
found two tools for Verilog which is supposed to keep documentation
and implementation of control and status registers in sync. Vregs on
www.veripool.com and csrGen.pl on asics.chuckbenz.com....default modelsim vsim options for verilog simulation [2 articles]
nachum - 2009-07-03 12:40:00
How can I tell Modelsim that when I right-click and choose Simulate it
should automatically search certain libraries. For example I'm using
Xilinx libs, and I need it to run like this:
vsim -L xili...DDR2 IPCore implementation problem based on MIG2.3
vcar - 2009-07-03 11:54:00
In my design, I used the MIG2.3 DDR2 IP Core. In customization, I
chose not to include the DCM inside, and I provide all the necessary
clocks needed by the IP Core.
Now the problem comes at the PAR...