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Comp.Arch.FPGA
Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.
There are 16332 threads in our archives.
You are looking at page 1 of 1634.
The threads with the newest articles are listed first.
Compiling a design in Quartus that doesn't fit
General Schvantzkoph - 2010-03-11 10:05:00
I want to be able to generate an encrypted netlist of a core using
Quartus. Does Quartus have a switch that allows you to compile a design
that doesn't fit into an FPGA? The issue is that the port...
Tier Logic introduces the world's first 3D FPGA [18 articles]
Tier Logic - 2010-03-11 09:32:00
The world's first 3D FPGA has arrived! We have a very compelling and
cost effective solution.
Come check it out folks. www.tierlogic.com
Jeff
...Why doesn't this situation generate a latch? [14 articles]
Weng Tianxiang - 2010-03-11 06:48:00
Hi,
I have a question about when to generate a latch.
In Example_1 and Exmaple_2, I don't think it will generate a latch. I
don't know why.
Example_1: process(RESET, CLK)
Begin
If RESET =3D...Some Active-HDL questions [17 articles]
Pete Fraser - 2010-03-11 05:42:00
I have an evaluation copy of Active-HDL, and am having
some (presumably) newbie issues with it.
I went through their VHDL tutorial, but it has all sorts
of visual editors in the flow that I'm not...Spartan3AN DDR2 - bad writing zeros [8 articles]
lusch - 2010-03-11 05:36:00
I've got a problem with my DDR2 (MT47H32M16) on my Spartan3AN board. I
use MIG 2.3 controler. The burst lenght is 4. When I'm writing the
data like x"A1A1B2B2" or x"01010101" everything works. I'm r...Tabula. (FPGA start up) [26 articles]
Symon - 2010-03-10 22:08:00
This lot seems to be revealing a bit more about their stuff.
http://www.mercurynews.com/breaking-news/ci_14493616
http://www.tabula.com
...Xilinx ISE Webpack Schematics
TudaPellini - 2010-03-10 19:23:00
Hi ASICFriends,
I'm using XILINX ISE WebPack, release 8.2 (due to compatibility issues
with older projects).
Does anyone know how to make some symbol inputs to be "don't care"
inside an ISE sche...Translate Error: ngd build 604 [2 articles]
Pallavi - 2010-03-10 18:30:00
Hi, I'm doing this project using ISE 9.2i and am getting the ngd build
error: 604 during translation. Can anyone please let me know how to resolve
this error. I'm able to synthesize the code successfu...using an FPGA to emulate a vintage computer [235 articles]
Eric Chomko - 2010-03-10 14:30:00
Has anyone created a copy machine of an old system using an FPGA? I
was wondering if it would be possible to take an entire SWTPC 6800 and
compile the schematics and have it run on an FPGA board.? W...Modelsim PE vs. Aldec Active-HDL (PE) [38 articles]
Pete Fraser - 2010-03-09 20:27:00
I've finally decided to buy a better simulator
(I've been making do with Modelsim XE so far).
Any thoughts as to the relative merits of Modelsim PE and
Active-HDL (PE) for FPGA simulation?
Tha...