Comp.Arch.FPGA interface on FPGARelated
Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.
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Posted by rashmic - 2 days ago
I am working on Xilinx Spartan 3e Starter kit board which has DDR Ram. I have to transfer image file to DDR and store it for further manipulation using EDK.Please provide different techniques t...
Posted by Leo - 2 days ago
Hello, I want to send a pulse from one clock domain to another, knowing tha=
t from the time event that this pulse is generated in the source clock doma=
in it arrives in the first rising edge of th...
Posted by Svenn - 2 days ago
I am trying to create a comparison list between various FPGAs in the
Xilinx universe. The unisim library lists all primitives, but not all of
the primitives listed in unisim are available in ...
Posted by Rob Gaddi - 3 days ago
So, the following ROM initialization code should be entirely
synthesizable. Not so, according to the latest version of Vivado,
which proudly declares "ignoring unsynthesizable construct:
Posted by Vladimir Ivanov - 4 days ago
What are the practical pros and cons of using each of ISE or Vivado for
the Artix-7 family?
I am interested in the basic synthesis/map/routing/STA steps. Aside from
possible speed i...
I'm using XST 14.2 and trying to use block RAMs to store constant data
(i.e. as ROMs) for program code that will be run by a CPU. I want to
infer the block RAMs during synthesis and then ac...
Posted by Abdulla873 - 4 days ago
Are there any differences between instantiating components and using
generate statement in hierarchical structure design??
Posted by kaz - 4 days ago
TimeQuest says it uses two hold checks per each setup check. The first hold
previous latch edge with current launch edge and second check for current
with next launch e...
Posted by Simon - 1 week ago
So I wanted to know if it was possible to update an old embedded-developmen=
t kit license that's expired. There's nothing on xilinx' site as far as I c=
an see that allows for old licenses to be ...
Posted by Michael - 2 weeks ago
I have a Altera Cyclone II design where I am looking for a good way to
make a complete reset via HDL.
In Xilinx there is a STARTUP macro that can be used for reset, does the
Altera also ...