Sign in

Not a member? | Forgot your Password?

Search Comp.Arch.FPGA

Search tips

Recent Blogs on FPGARelated

I don’t often convert VHDL to Verilog but when I do ...
posted by Christopher Felton

Spline interpolation
posted by Markus Nentwig

BGA and QFP at Home 1 - A Practical Guide.
posted by Victor Yurkovsky

Introducing the VPCIe framework
posted by Fabien Le Mentec

How FPGAs work, and why you'll buy one
posted by Yossi Kreinin

Learning VHDL - Basics
posted by Enrico Garante

Yet another PWM
posted by Anton Babushkin

Two jobs
posted by Stephane Boucher

How to start in FPGA development? - Simulation software tools
posted by Nuria Orduna

An Editor for HDLs
posted by Dave Vandenbout

See Also

DSPEmbedded Systems

Comp.Arch.FPGA interface on FPGARelated

Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.

There are 17959 threads in our archives.

You are looking at page 1 of 1796.

The threads with the newest articles are listed first.

Program Xilinx with Altera JTAG Programmer? [12 replies]

Posted by jackm - 14 hours ago

Hello, I am looking for an ultra-cheap way to program Xilinx CPLDs and FPGAs. On Ebay they sell Altera USB Blaster JTAG programmers that ship from China and are fake copies I assume, they cost less ...Program Xilinx with Altera JTAG Programmer?

Microblaze problem with FSL core [2 replies]

Posted by hafezmg48 - 3 days ago

Hi guys, I'm not sure this is the right place to ask this question, but I found no answers to it on xilinx forums. Hope you can help me! intro: I work with atlys board. using Microblaze proc...Microblaze problem with FSL core

An Altera CPLD "JTAG Unlocker"

Started by Unknown 4 days ago

Hi There, From time to time I see people having Altera CPLDs on the "JTAG Lockout" st= atus. I have a few EPM7128s on this state myself. I wonder how difficult would it be to create a...An Altera CPLD "JTAG Unlocker"

New invention: Systematic method of coding wave pipelined circuits in HDL

Posted by Weng Tianxiang - 5 days ago

Hi Jim, glen, JK, rickman, Mike, Andy,=20 I have filed a provisional patent application: "Systematic method of coding= wave pipelined circuits in HDL". If it is proved correct, the pate...New invention: Systematic method of coding wave pipelined circuits in HDL

FPGA Project - [3 replies]

Posted by Julian Gardner - 5 days ago

Looking for someone to work on a project. Quick Notes 1. PCI FGPA Card (standard off the shelf is possible) 2. Interface to decryption engine 3. Multiple decryption engines, as many as the FPG...FPGA Project -

Inferring F7 / F8 Mux in Xilinx [2 replies]

Posted by Kevin Neilson - 1 week ago

I'm posting this here for my own future reference. If you infer a mux with fewer than 2**n inputs, Vivado won't infer the F7 or F8 muxes. Here is the trick to make sure you get the best synthesis....Inferring F7 / F8 Mux in Xilinx

Open Source GPGPU core [9 replies]

Started by Unknown 1 week ago

I've been designing an open source Larrabee-esque GPGPU processor in System= Verilog and I thought people might find it interesting. Full source code, d= ocumentation, tests, tools, etc. are availab...Open Source GPGPU core

Kintex UltraScale board with two DDR4 interfaces?

Posted by Owenh - 2 weeks ago

Hello, I am looking for a Xilinx Kintex UltraScale FPGA board, where it would be possible to run two separated DDR4 controllers (i.e., a board where there is more than one address bus for the DDR4 ...Kintex UltraScale board with two DDR4 interfaces?

Dynamic partial reconfiguration on Spartan 3 chips [2 replies]

Started by Unknown 2 weeks ago [ Spartan | Spartan3 | Xilinx ]

Well it finally worked for me. i had many problems especially with the PAR tool of Xilinx ... Thanks for all those who helped me with my questions .. (thanks Dirl , thanks Antti ..) Recobus ...Dynamic partial reconfiguration on Spartan 3 chips

processor core validation [2 replies]

Posted by alb - 2 weeks ago

Hi everyone, I was wondering if anyone can point me to some formal method to validate a soft processor core. We have the source code (vhdl) and a simulation environment to load programs and...processor core validation

| 1 | | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 |