Comp.Arch.FPGA interface on FPGARelated
Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.
There are 17739 threads in our archives.
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Posted by Aleksandar Kuktin - 17 hours ago
Some time ago, I designed a small and simple CPU to go into a project I
am sort-of working on (when can I steal the time to do so). Now, I added
an interrupt mechanism to it and encount...
Posted by Gergo - 2 days ago
I'd like to use my MachXO Breakout Board as a programming device to program a custom MachXO chip on a board. Is that possible at all? I could not find anything useful in the board's user guide....
Posted by Tung Thanh Le - 4 days ago
I got a problem that I cannot understand how to display on the LCD of Sp=
artan 3E FPGA. Then, how to get the inputs and outputs of a 16-bit Ripple C=
arry Adder to show on LCD? Please any ...
Posted by John Larkin - 4 days ago
We're into this signal processing project, using a microZed/ZYNQ thing as the
After a week or so of work by an FPGA guy and a programmer, we can now actually
read and write an...
Posted by Wojciech M. Zabolotny - 1 week ago
I was solving a problem, when I needed to calculate every clock a sum of multiple values
encoded on a small number of bits (the latency of a few clocks is allowed).
A natural solution seemed to be...
Posted by beginner - 1 week ago
1.sorry for my poor english
2.i have the following diagram to implement in verilog: http://elf.cs.pub.ro/ac/wiki/_media/teme/tema2/tema_2_top_module_instance.png
I want to make an synchrono...
Posted by youngejoe - 1 week ago
Proposed idea from my research to date:
Two FPGA encryption modules: Both will have an identical encryption algorit=
hm; key management something I need to research further.
Bob has pl...
Started by Unknown 2 weeks ago
If you are making VHDL testbenches you should be writing proper log message=
s. You should also make your result-checkers properly report mismatches and=
also allow positive acknowledge. Equally im...
I'm playing with the idea of interfacing a BeagleBone
(cheap dual ARM Cortex A8 board) to a Xilinx KC705
Kintex development board. This will give me much more
CPU processing power than a microblaze...
I've been wondering if there could be a successful (not too large,
reasonable clock frequency) soft-core FPGA version of a low end variant of
the Mill. One issue with FPGAs is that only two-port me...