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Recent Blogs on FPGARelated

Point of View
posted by Christopher Felton

Spline interpolation
posted by Markus Nentwig

BGA and QFP at Home 1 - A Practical Guide.
posted by Victor Yurkovsky

Introducing the VPCIe framework
posted by Fabien Le Mentec

How FPGAs work, and why you'll buy one
posted by Yossi Kreinin

Learning VHDL - Basics
posted by Enrico Garante

Yet another PWM
posted by Anton Babushkin

See Also

DSPEmbedded Systems

Comp.Arch.FPGA interface on FPGARelated

Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.

There are 17910 threads in our archives.

You are looking at page 1 of 1791.

The threads with the newest articles are listed first.

XILINX PCIe read of slow device [16 replies]

Posted by David Binette - 2 hours ago

What is the correct way to handle a PCIE request to a slow device? I have a xilinx spartan 6 PCIe using Integrated Block for PCI Express. The BAR memory map is decoded and some addresses map to ...XILINX PCIe read of slow device

looking for dev kit for ProAsic3 [7 replies]

Posted by alb - 1 day ago

Hi everyone, I'm looking for a dev kit for a ProAsic3 A3PE3000 (microsemi) with some minimum amount of functional blocks around (volatile/non-volatile memory, few peripherals like UART, USB, SP...looking for dev kit for ProAsic3

The EDIF variant used by fit150X.exe [1 replies]

Posted by Johann Klammer - 2 days ago

Can anyone point me to samples of the edif variant accepted by the atmel PLD fitters? Google can't seem to find any, and their free CUPL seems to generate .PLA things only. ...The EDIF variant used by fit150X.exe


Posted by mnentwig - 3 days ago

Hi, does anybody know whether it is possible (or impossible) to use an FPGA's serial transceivers for a MIPI type 2 M-PHY link (i.e. 1.5 GBit/s)? Xlinx' book M-PHY and FPGA?

USB PHY recommendations [4 replies]

Posted by Mike Perkins - 7 days ago

I have started using the TI TUSB1210 which is a USB PHY with a ULPI interface. However, I can virtually guarantee that during enumeration, the device will lock up with DIR permanently DIR hig...USB PHY recommendations

[cross-post] verification vs design [8 replies]

Posted by alb - 1 week ago

Hi everyone, I've recently had to argue why it is not 'sane' to budget 500 hours of development against 200 of verification. If you ask the FPGA developer he'd say a factor of 2/3 has to be ...[cross-post] verification vs design

Altera 100-pins chip [2 replies]

Posted by Rego - 1 week ago

Hello, I'm looking for suggestions for an Altera 100-pins chip which I can use in a board like this 100-pins chip

Non-project mode Vivado simulation? [4 replies]

Started by Unknown 1 week ago

Is it possible to run a Vivado simulation in non-project mode? I can't seem to find any documentation on how to do it. ug835 describes which Tcl commands are used for simulation, but not whic...Non-project mode Vivado simulation?

Fast and slow clocks [10 replies]

Started by Unknown 2 weeks ago

I'm wondering what the correct way to handle the following situation is. Sorry this is a bit long winded. BTW, it's not homework, all that was 40+ years ago. I have two clocks, clk which is the...Fast and slow clocks

Need ideas for FYP [25 replies]

Started by Unknown 2 weeks ago

I am student of Bachelors and going to start my FYP in some days. I am going into the field of high computation in verilog. These are some projects which I might be doing: 1.the n-body gravitational ...Need ideas for FYP

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