Comp.Arch.FPGA interface on FPGARelated
Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.
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Posted by jackm - 14 hours ago
I am looking for an ultra-cheap way to program Xilinx CPLDs and FPGAs. On Ebay they sell Altera USB Blaster JTAG programmers that ship from China and are fake copies I assume, they cost less ...
Posted by hafezmg48 - 3 days ago
I'm not sure this is the right place to ask this question, but I found no
answers to it on xilinx forums. Hope you can help me!
I work with atlys board. using Microblaze proc...
Started by Unknown 4 days ago
From time to time I see people having Altera CPLDs on the "JTAG Lockout" st=
atus. I have a few EPM7128s on this state myself.
I wonder how difficult would it be to create a...
Posted by Weng Tianxiang - 5 days ago
Hi Jim, glen, JK, rickman, Mike, Andy,=20
I have filed a provisional patent application: "Systematic method of coding=
wave pipelined circuits in HDL". If it is proved correct, the pate...
Posted by Julian Gardner - 5 days ago
Looking for someone to work on a project.
1. PCI FGPA Card (standard off the shelf is possible)
2. Interface to decryption engine
3. Multiple decryption engines, as many as the FPG...
Posted by Kevin Neilson - 1 week ago
I'm posting this here for my own future reference.
If you infer a mux with fewer than 2**n inputs, Vivado won't infer the F7 or F8 muxes. Here is the trick to make sure you get the best synthesis....
Started by Unknown 1 week ago
I've been designing an open source Larrabee-esque GPGPU processor in System=
Verilog and I thought people might find it interesting. Full source code, d=
ocumentation, tests, tools, etc. are availab...
Posted by Owenh - 2 weeks ago
I am looking for a Xilinx Kintex UltraScale FPGA board, where it would be
possible to run two separated DDR4 controllers (i.e., a board where there
is more than one address bus for the DDR4 ...
Well it finally worked for me. i had many problems especially with the
PAR tool of Xilinx ...
Thanks for all those who helped me with my questions .. (thanks Dirl ,
thanks Antti ..)
Posted by alb - 2 weeks ago
I was wondering if anyone can point me to some formal method to validate
a soft processor core.
We have the source code (vhdl) and a simulation environment to load