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Recent Blogs on FPGARelated

[Comments] C HLS Benefits
posted by Christopher Felton

Signed serial-/parallel multiplication
posted by Markus Nentwig

BGA and QFP at Home 1 - A Practical Guide.
posted by Victor Yurkovsky

Introducing the VPCIe framework
posted by fabien le mentec

How FPGAs work, and why you'll buy one
posted by Yossi Kreinin

Learning VHDL - Basics
posted by Enrico Garante

Yet another PWM
posted by Anton Babushkin

See Also

DSPEmbedded Systems

Comp.Arch.FPGA interface on FPGARelated

Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.

There are 17812 threads in our archives.

You are looking at page 1 of 1782.

The threads with the newest articles are listed first.

more than 58'000 false paths... [7 replies]

Posted by alb - 12 hours ago

Hi everyone, I started adding false paths to my design (see this thread for a context: ) but in order to avoid funny names, I started to add wildcards. My false path constraints look like ...more than 58'000 false paths...

how to specify which feature for a license

Posted by alb - 24 hours ago

Hi everyone, we have a license server that hosts both ACTEL_SUMMIT feature (1 seat) and ACTEL_VISTA one (10 seats). Is there a way in Designer to specify either from the command line or to specify which feature for a license

[cross-post] group on systemC language [7 replies]

Posted by alb - 1 day ago

Hi everyone, does anyone out there know a group specialized on systemc? I'm interested in tlm modeling and platform virtualization. Thanks in advance, Al -- A: Because it messes up the...[cross-post] group on systemC language

Help: Altera megafunctions, Quartus II [2 replies]

Posted by Bruce Varley - 1 day ago

I'm an FPGA newbie, working with the freeware Altera Quartus II IDE. I used the megafunction builder to create a FIFO memory, the .v file it generated is similar to the virtual prototypes created ...Help: Altera megafunctions, Quartus II

Actel Designer on multiple cores [3 replies]

Posted by alb - 2 days ago

Hi everyone, I had my vbox running with one core only (out of 4 on the host) and Designer was running extremely slow, so I thought 'what the heck' I'm not doing much with the other 3 cores on m...Actel Designer on multiple cores

cloud design flow [16 replies]

Posted by alb - 2 days ago

Hi there, I was wondering if there's any one out there working with a cloud design flow which is tool agnostic. The reason for asking is that I'm trying to evaluate if there's a way to design flow

on-chip bypass caps [25 replies]

Posted by John Larkin - 3 days ago

I got a spreadsheet from Altera that lists the on-chip power supply bypass caps on an Arria II GX95 FPGA. I was kind of shocked to see 32 listed capacitors, most around 1 nf, but a Vcc_core (0.9...on-chip bypass caps

static timing analysis [1 replies]

Posted by alb - 5 days ago

Hi everyone, any good reference on STA? I know roughly well the principles but I've always wanted to get a deeper understanding of this - vast - subject, especially the algorithms behind it. ...static timing analysis

Lattice MachXO3L - is it available anywhere ? [12 replies]

Posted by Brane2 - 5 days ago

I've downloaded documetnation on lower part of newcomers - MachXO3. New Diamnond 3.1 has support for chips, but I can't find chips anyhwere. I tried Farnell and Mouser and couple of other adres...Lattice MachXO3L - is it available anywhere ?

Call for designs ("give us your timing, your synthesis/par problems, your huddled critical paths yearning to breathe free")

Started by Unknown 5 days ago

Learning about and working with FPGAs, many times I've wondered if there is= a common pool of design knowledge and best practices that I can refer to, = especially when facing a particular tough cr...Call for designs ("give us your timing, your synthesis/par problems, your huddled critical paths yearning to breathe free")

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