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Comp.Arch.FPGA


Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.

There are 16714 threads in our archives.

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The threads with the newest articles are listed first.

Xilinx Series 7 device availability [9 articles]

Roger - 2010-09-03 08:53:00
I thought that the Series 7 devices would be available in Q1 2011 but have recently heard they'll be badly delayed until at least Q3. Does anyone else have any information as to when I'll be able ...Xilinx Series 7 device availability

debit source code

Charunethran - 2010-09-02 21:57:00
Hey, I was going through debit to experiment with bitstream formats. Apparently the site (www.ulogic.org) seems to be down and I couldn't get the source code by that time. Does anyone have the so...debit source code

Want to get into FPGA [5 articles]

RealInfo - 2010-09-02 18:56:00
Hi all I am a 52 years old electronics technician with massive experience in analog electronics like audio and power supplies . I want to start a career in FPGA designing . My intention is to ...Want to get into FPGA

dct verilog [4 articles]

Shakes - 2010-09-02 18:29:00
hi, I downloaded the DCT verilog module from the altera website. http://www.altera.com/support/examples/verilog/ver_dct.html I ran a simulation using simple testbench that sends 0,1,2,...63 as ...dct verilog

parsing script arguments in QuestaSim/ModelSim [4 articles]

Marcin Rodzik - 2010-09-02 17:37:00
I have a problem with an automated testbench in ModelSim/QuestaSim. I run a TCL script which invokes another script using the DO command. In the other script, I use both SWITCH and SHIFT commands to...parsing script arguments in QuestaSim/ModelSim

Tutorial on timing constraints

Mike Santarini - 2010-09-01 14:43:00
Xilinx Guru Austin Lesea penned a great tutorial on timing constraints in the latest issue of Xcell Journal. Here is a link to the flash version http://cde.cerosmedia.com/1G4c56e6f64dfe8012.cde/page...Tutorial on timing constraints

BRAM initialization in EDK 12.2

Plutonium - 2010-08-31 17:29:00
Hi! Xilinx changed BRAM initialization process in EDK 12.2. There is no system_conf configuration. Now EDK use mem-files to init BRAMs. In my project they are filled with data, but in Modelsim or Is...BRAM initialization in EDK 12.2

FPGA DAC Interface [5 articles]

Sharath Raju - 2010-08-30 19:10:00
Hello everyone, We are building a board in which we propose to design the FPGA interface to a DAC in the following manner. Please give feedback whether such an approach is feasible. Functional...FPGA DAC Interface

Plotting sampled data in Matlab [12 articles]

Pete Fraser - 2010-08-29 05:13:00
I'm simulating some filter hardware in Modelsim, and need a way to display the output with a virtual anti-alias filter. Is there a Matlab facility for this? plot doesn't seem to have any good opt...Plotting sampled data in Matlab

Stratix iv PLLs ref clock [4 articles]

kadhiem_ayob - 2010-08-28 14:09:00
Hi All, My design is meant to work at two speed modes(full & half rate). Initially I used one clk source(560MHz) plus enable. However, I envisage changing the plan to divide the clk itself from o...Stratix iv PLLs ref clock
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