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Spline interpolation
posted by Markus Nentwig


[Comments] C HLS Benefits
posted by Christopher Felton


BGA and QFP at Home 1 - A Practical Guide.
posted by Victor Yurkovsky


Introducing the VPCIe framework
posted by Fabien Le Mentec


How FPGAs work, and why you'll buy one
posted by Yossi Kreinin


Learning VHDL - Basics
posted by Enrico Garante


Yet another PWM
posted by Anton Babushkin




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DSPEmbedded Systems

Comp.Arch.FPGA interface on FPGARelated

Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.

There are 17870 threads in our archives.

You are looking at page 1 of 1787.

The threads with the newest articles are listed first.

Primitive debuggable UART interface to a Nios within a multi-Nios system [8 replies]

Posted by Ang Zhi Ping - 13 minutes ago

I am working on an IP core with a Nios controller. This IP will eventually be integrated into a multi-Nios system. I also foresee that this IP will not be JTAG debuggable because the integrator wi...Primitive debuggable UART interface to a Nios within a multi-Nios system

Generating a desired synthesizable binary pulse train on FPGA using VHDL [21 replies]

Posted by chaitanya163 - 1 day ago

Hello Everyone I am new to VHDL programming and FPGA. I have a Virtex - 4 FPGA and I wish to generate a binary pulse train of 16 pulses from FPGA using VHDL programming. My desired pulse train ...Generating a desired synthesizable binary pulse train on FPGA using VHDL

Know any good public FPGA projects to contribute to? [3 replies]

Posted by signaltap - 4 days ago

Hi all, Can you suggest any good FPGA projects I could contribute to? I have some = free time and want to work on something challenging and interesting. Inste= ad of starting something myself I...Know any good public FPGA projects to contribute to?

Chisel as alternative HDL [52 replies]

Posted by Martin Schoeberl - 4 days ago [ Verilog | VHDL ]

Hi all, started to look into alternatives to Verilog and VHDL and stumbled over chisel from UCB: http://chisel.eecs.berkeley.edu/ Any experiences and comment on this language? Looks like so...Chisel as alternative HDL

Help with Address load logic [7 replies]

Posted by Syed Huq - 2 weeks ago

Hi, I'm trying to implement a trigger with 2 BRAMs with one BRAM storing all th= e data samples from the ADC and another BRAM just transferring samples from= the 1st BRAM to the 2nd on the event...Help with Address load logic

vmWare supporting Avnet Virtex-5 PCIe board [1 replies]

Posted by maverick - 2 weeks ago

Hi, I am planning to install vmWare on one of my server machines and create virtual servers on it. I need to access a Virtex 5 PCIe board from Avnet from the virtual environment. Q1. Does vmWare su...vmWare supporting Avnet Virtex-5 PCIe board

Using FPGA as dual ported ram [29 replies]

Posted by Stef - 2 weeks ago

To interface a fast sampling ADC to a CPU I'm considering to use a fifo or dual ported ram and a small controlling CPLD. Cypress has a nice offering of fifos and dp-rams, but looking at the prices o...Using FPGA as dual ported ram

CFP: EECEA2014 Malaysia

Posted by Hazel Ann - 2 weeks ago

The International Conference on Electrical, Electronics, Computer Engineering and their Applications (EECEA2014) Asia Pacific University of Technology and Innovation (APU), Kuala Lumpur, Malaysia ...CFP: EECEA2014 Malaysia

CFP: The International Conference on Electrical, Electronics, Computer Engineering and their Applications (EECEA2014) Malaysia

Posted by Hazel Ann - 2 weeks ago

The International Conference on Electrical, Electronics, Computer Engineering and their Applications (EECEA2014) Asia Pacific University of Technology and Innovation (APU), Kuala Lumpur, Malaysia ...CFP: The International Conference on Electrical, Electronics, Computer Engineering and their Applications (EECEA2014) Malaysia

wishbone bus between two fpgas [4 replies]

Posted by alb - 3 weeks ago

Hi everyone, we are in the preliminary phase of the architecture definition for our system and we estimated FPGA resources (for a particular target) to be ~80% of the target's capabilities. ...wishbone bus between two fpgas

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