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ASIC
Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.
We found 891 threads matching "asic"
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The most relevant threads are listed first
FPGA -> ASIC
Ted Lechman - 2004-09-25 16:40:00
How do I take an exisiting FPGA design ( say a xilinx Spartan IIE or III,
designed in vhdl, simulated in ModelSim and is presently running
successfully in an FPGA ) and cost reduce it as an ASIC:
1. What type of quantities are needed to make ASIC viable
2. Please name a couple of ASIC houses t...
How to interface ASIC on a PCB and and an FPGA
Biswajit Mishra - 2006-03-06 05:08:00
Hi,
I have a custom ASIC and I would like to interface this with my XUP V2P
(Xilinx
VII Pro) board. I am new to using the Xilinx boards. Please suggest a simple
way to generate a clock from the FPGA and few synchronised control signals
with
this clock. I have to feed the clock and the contro...Cost to go from FPGA to ASIC
Bob - 2005-10-27 01:03:00
How much does it cost to produce an ASIC? This is for a
simple customized 8-bit CPU and 64KB of on-chip RAM.
If it is already working in an FPGA, can I count on the
ASIC also working?
Can I just hand the VHDL/Verilog files to the fabricator? Or
should I change the design to take advantage ...FPGA Vs ASIC design and implementation
Karl - 2007-03-07 17:30:00
Hi,
Being familiar with FPGA design and implementation flow and illiterate
with ASIC corresponding one. My question is the following
what are the main similarities/differences between designing and
implementing an algorithm on these two different targets? in
particular what are the design/i...ASIC Prototyping
ASPENLOGIC - 2009-11-30 10:55:00
I've started a new ASIC Prototyping group on LinkedIn. To join, search
for "ASIC Prototyping" in the groups directory.
...From ASIC RTL to FPGA, what are the things I should take care of?
jasonL - 2008-02-20 12:00:00
I have a project to prototype an ASIC design on FPGA. What are the
things I should do? Here is some of my concerns:
1) I understand FPGAs usually have 4 look-up table. Should I rewrite
the ASIC combinational logics to be four-inputs logics to improve the
utilization of FPGA?
2) Netting if a...ASIC Prototyping
2008-09-13 02:10:00
Hi
I am new to ASIC prototyping approaches. I know it concept wise but
want to know more about how popular is it among designers. In other
words, is it a commonly taken path for verification or is more of a
concpet than having practical applictaions.
I also want to know if there are any too...FPGA-ASIC Migration
Venkat - 2008-12-08 19:50:00
Hello all,
I have a question regarding migration of design from Xilinx FPGA to
ASIC. There are lot of Xilinx IP Cores(I am sure even Altera will have
too) which are commonly used for Arithmetic Purposes. For instance my
design uses the Xilinx FFT/IFFT IP Cores and if the design has to be
move...FPGA vs. ASIC vs. Processor
2005-06-24 11:10:00
Hi all, I'm doing a project on "VHDL implementation of LOG CFAR". I
need somebody to enumerate the differences FPGA vs. ASIC and FPGA vs.
Processor. I dont have much idea on ASIC and am still learning about
FPGA.
Thanx
...How to connect FPGA to a ASIC Board?
2008-02-27 04:42:00
Hello Techies,
I would like to use an off the shelf FPGA which I would be develpoing
to test an ASIC or other FPGA. My questions is,
1. How do we connect the Output of FPGAs as Input of the ASIC and vice
versa?
2. The FPGA has to check various protocols like SPI, UART and other
things?
I ...ASIC from working FPGA design
2009-04-29 13:08:00
Hi
I'm considering the option of converting an FPGA design into ASIC, but
have no experience with that. My questions are:
1) Cost savings, how do ASICs compare to FPGAs?
2) Given VHDL that works on FPGA, will there be considerable risk
associated with the ASIC conversion?
3) How long ...ASIC speed
Yu Jun - 2003-11-06 21:48:00
I'm working on a cpu core and intend to embed it into ASIC circuits,
with the aim to do some network processing. Now the FPGA prototype is
running and a 66M speed is achieved( xilinx virtexII-4 ). Wondering
how fast it can run in ASIC, we had our ASIC guys to synthesize the
codes and the result ...asic vs fpga comparison issues
paraag - 2004-01-22 20:21:00
Hi
How do i compare asic power/timing features for the same design with
an FPGA having that same design....i mean what tecnology does xilinx
use to fabricate their die ,
The Xpower readings from the ISE foundation gives an estimate of power
, but i would like to know with which asic flow is...ASIC Prototyping using FPGA
Test01 - 2009-10-09 17:15:00
I am trying to understand if there is a well defined procedure to do
ASIC prototyping using FPGA. I was thinking that I can divide down
the ASIC design into multiple functional blocks. Such that each block
represents asn ASIC. The design is in verilog HDL but it contains a
lot ASIC lib specifi...Looking for Rapid prototyping system, ?Quickturn ASIC-Emulator?
Ken - 2005-05-11 21:43:00
Hello all,
I am responsable to purchase and set up a electonics prototyping
system for my university. The price is not a issue but the major
concern is that the system should be easy to set up. (preferably a
one-whole unit or a few modules)
I have done some search in the web, it seems the '...ASIC suggestions
dave94024 - 2005-08-10 19:34:00
We're about to move an existing design to an ASIC. The prototype was
built using a small PIC and some discretes, so the ASIC will look
nothing like the prototype.
I'm looking for some suggestions for ASIC design house people have used
and been happy with as well as ASIC design services (someo...ASIC vs FPGA
newbie - 2003-11-09 13:59:00
Hi all
Can someone help in understanding the main difference between ASIC and FPGA.
I keep hearing both these terms and am not fully clear.
Is there a website explaning this?
Thanks
...FPGA to ASIC migrate
Jerzy Gbur - 2006-02-22 13:46:00
Hi
I'm looking for possibilities for migrating project/design from
FPGA(XC2V3000) to any asic.
What companies, have you ever had experience in this field?
Kind regards.
Jerzy Gbur
...FPGA -> ASIC`
Eli Hughes - 2006-01-06 10:12:00
Hello:
I have absolutely no experience in ASIC design. I do however have
experience in FPGA. I have a CPU design that is currently working in a
Xilinx FPGA. The design fits in a spartan3 XCS200 (144pin Package).
I want to migrate to a fully custom chip in a different package. My
desi...What is the difference between ASIC and FPGA?.
2005-01-15 20:02:00
Hello, I have two questions about Electronic circuit board design.
These are the questions:
1st question:
What is the main difference between FPGA and ASIC, recently I went to
some exhibition, there I heard from somebody, he says "we are designing
a prototype handset based on FPGA, which was ...Equivalent ASIC Gate Estimate
Venkat - 2008-12-04 19:41:00
Hello all,
Is there a way (even a rough approach) of finding an equivalent
estimate of ASIC Gates for the design implemented in Xilinx FPGAs
considering their definitions of Slices, DSPs and BRAMs? I know the
approximate conversion ratio between ASIC and FPGA gates is 1:5, but
way of identify...Asic prototyping in Fpga - prototyping the gates.
gretzteam - 2005-01-20 12:11:00
Hi,
We are currently using virtexIIpro and virtex4 fpga to prototype a dsp
processor. All the code is synthesizable verilog and we are using
Xilinx ISE to do synthesis and place and route. Everything works fine
and the processor runs at full speed (50Mhz). However, this is only
good for functio...ASIC design
Christian Haase - 2004-05-04 09:20:00
Hello,
are there any valuable sources (links, papers, books) that
guide to ASIC design? (esp. synthesis + implementation e. g.
with the Cadence tools).
Thanks a lot for any kind of interesting advice
Christian
...32 bit multiplier
VIPS - 2008-04-08 14:48:00
Hi All
This application I am looking at requires 17 tera bytes of
multiplication per second. Which in an FPGA means 40K FPGAs. What I
want to know is how many 32x32 Mults can you fit into an ASIC today
Standard Cell or Custom ASIC. Also what kind of speeds can I get.
Bye
vipul
...I/O Pads in ASIC
designer_india - 2009-07-02 09:13:00
Hi
How we will convert I/O pads in ASIC to FPGA ( Virtex-5 ). If we have
around 200 I/O pads how will do .
Pls give me some reference reading for this conversion.
THanks
Pradeep
...How is FIFO implemented in FPGA and ASIC?
Wei Wang - 2008-01-18 08:48:00
Hi,
Could anyone explain why FIFO is difficult to implement in FPGA and
ASIC? and how is FIFO implemented in FPGA and ASIC.
Thanks,
Wei
...asic gate count
vijayant.rutgers@gmail.com - 2008-04-15 16:23:00
hi,
i have got xilinx fft IP core from coregen. Is there any way that i
can get asic gate count for this ? Any help / hint is greatly
appreciated.
thanks,
vijayant.
...another FPGA/asic vendor dead :(
Antti Lukats - 2005-10-27 14:25:00
NEWS: LeopardLogic has ceased operations. It wasnt directly FPGA but rather
asic with part of it as configurable fpga fabric.
Cypress is also out of PLD business silently, well that was to be expected.
humm, who is next?
antti
...Hardcopy Vs ASIC
2005-02-21 06:19:00
I was going through the hard copy product from altera. Methodology
seems really promising. I just wonder where hard copy products stands
as compare to ASIC wrt performance, power, yield & Time to market
...Structured ASIC players
John_H - 2007-02-22 18:10:00
NEC will exit the structured ASIC business
http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=197008125
Is that 2 major players gone? How many more are there?
- John_H
...Conversion of ASIC RTL to FPGA RTL
sarath - 2005-07-27 02:02:00
Hi all,
Can any one list me out the various steps that need to be carried
out to convert ASIC RTL Code to FPGA RTL Code. In what way the ASIC RTL
Code differs from FPGA RTL Code. Can you also list me the various tools
that are available to perform them.
Thanks in Advance,
Sarath
...FPGA to ASIC conversion
shruti - 2009-08-20 08:48:00
Hi,
I need to convert my fpga based designs to make an asic.I am entering into
this area first time so i wanted to know the design issues, tools, vendors
who provide this service and cost aspects for this process.
If you can help me in this regard then I will be really thankful.
Thanks in advance...SOC and ASIC ?
Muthu - 2004-08-28 07:00:00
Hi,
Can any help me out to understand, how does SOC differs from ASIC ?
-Muthu.
...Memory gate count in ASIC and in FPGA
2005-03-15 08:52:00
Is the memory gate count in ASIC the same number as in FPGA? For
example I have 300Kbyte rom in ASIC needs to be implemented in Xilinx
FPGA, what the gate count in FPGA I expect?
THanks!
...Re: for all those who believe in ASICs....
Rob - 2006-03-09 00:12:00
Volumes and TTM (time to market) will dictate the path you take, either ASIC
or structure ASIC. And sometimes they both can work for you. We have a
recent product with projected numbers that make an ASIC the best candidate,
lowest UMC. The downside is that the ASIC has a long schedule; so l...ASIC vs FPGA and In-Circuit Reconfigurability (ICR)?
CraigR - 2004-09-30 13:16:00
In reviewing a specific requirement, my design team is debating the benefits
of in-field hardware upgradability. In the communications space, wondering
if most system developers require and use ICR in production when
implementing FPGA (instead of ASIC)?
Craig
...tools used for ASIC synthesis
teen - 2005-04-14 06:05:00
Hai all,
can you plz let me know the different tools used in industry
for ASIC SYNTHESIS
regards,
kishore
...ASIC vs DSP vs FPGA
crazyd - 2005-02-09 10:59:00
Hi,
I am looking for data showing typical development times for FPGA based
designs. I am trying to compare the cost of implementing a complicated
DSP system with different signal processing architectures. I have a
good idea of how long the development time would be for a progammable
DSP and...ASIC verification job info request
Dwayne Dilbeck - 2007-12-19 15:12:00
I am looking for a reality check. I have 10 years experience doing
software verification on EDA tools, in particular hardware emulators, System
Verilog, and VHDL. When looking at some job ads I see "required 6+ years
ASIC verification experience", can any of my 10 years experience be
convert...Reverse engineering ASIC into FPGA
Tobias Weingartner - 2005-04-04 11:49:00
Does anyone have experience with reverse engineering ASIC (black box)
into equivelant FPGA devices (pin equivelant with a sub-board if necessary)?
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