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CPLD
Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.
We found 873 threads matching "cpld"
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The most relevant threads are listed first
can JTAG port of CPLD gets damaged?
mohan - 2007-05-17 00:20:00
i am using altera cpld.using quartus 2 tool to programme it through
byte blaster cable.
I have installed drivers for the cable.made connections intact.
i am getting error as "Unable to scan device."
My assusmption was may be because of loose contacts this error was
coming.but connections are in...
24 to 32 8-bit PWM outputs
Emtech - 2005-10-24 06:24:00
I have an application where I need to implement 24 or up to 32 PWM outputs
(8-bit) and
am considering using a small CPLD to handle the PWMs instead of doing it all
in software.
This does add a CPLD to the design, but frees the micro do to other things.
Any recommendations on the CPLD & CPLD...max. sinking current of XC95144xl cpld
nishad - 2009-11-12 08:08:00
My requirement is to replace fifteen 7 segment display drivers using cpld
logic.
Total I/O connected to display will be 15*8=120.
Each pin has to sink around 8mA, so Im planning to go for Xilinx XC95288XL
CPLD.
My doubt is that can the cpld sink 120 lines of 8mA simultaneously?
...How to extend a pulse width without clock in CPLD!
peterzhu - 2003-09-04 02:13:00
Due to a chip bug, I have to extend a pulse width(negative)from 10ns
to 100ms in CPLD(Altera 7128). But the difficult is that I have no any
clock into the CPLD, so the CPLD is pure combination logic. how to
extend it in such case?
Help me!
...CPLD input
Hans Maier - 2004-04-25 18:22:00
Does a CPLD Input source current ? When I measure the voltage
at my CPLD input pin, it is somewhere in the 3V range. When I connect
it to ground, it sources about 50 mA. Is that normal ? I thought an
input should not behave like this ..!?
...Radiation + CoolRunner2 CPLD?
Bob - 2005-10-04 14:21:00
Hi I know that the CoolRunner2 CPLD TQ144, XC2C256-7TQ144I is not
designed to be radiation tollerent, but...
I would be interested if anyone reading this has ever radiated a CPLD
or know of some CPLD radiation data on the web.
I have google searched but found very little.
Most ics like 74hc04...CPLD development board with 8-bit wide Flash/EEProm
stevem1 - 2010-08-17 11:08:00
I have a custom 8051 RTL core that I want to put into a CPLD
on a development board.
I also need an external Flash/EEProm memory on the same
CPLD development board to run 8051 code from.
Are there any CPLD EVM/development boards that come with
an 8 bit with Flash/EEProm ?
If not I, I wil...CPLD erase??
2007-03-21 09:34:00
Working with a coolrunner2 CPLD. Is there a way to erase whatever has
been programmed into the CPLD, without using JTAG?
...FPGA vs CPLD
praveen - 2004-07-28 09:57:00
Hello,
What is the differences between FPGA and CPLD?
What basis on which i should select. whether to go for cpld or fpga?
waiting for reply
with regards
praveen
...delay using integrator
Sonali - 2006-02-16 06:11:00
I want to use the output of a R-C integrator as a delayed input to CPLD
(inside there is a XOR gate and counter logic). It worked OK when I use
discrete XOR IC 4070. But for same R-C values it doesn't works with
CPLD.
Is is due to the fact that analog input (sawtooth from integrator) has
given ...NVRAM design in CPLD
jay - 2008-06-27 00:21:00
Hi all,
For the ram implied in a CPLD design, will the data written in it
remain after power off?
I have a small rom in my curent CPLD design, occasionally I need
change the content inside, instead of reprogramming it, I want
something like a nvram that I can update through the uP dynamical...cpld 9572 xilinx
melvin - 2009-02-16 03:49:00
Currently i am doing my final year project on
xilinx cpld 9572
How do we can access registers in this cpld using vhdl .......
...min propagation delay in xilinx cpld
guille - 2004-01-08 04:16:00
Hi all,
I have a signal that originates at a given device with known timing
with respect to the rising edge of a clock: 2 ns min, 8 ns typ, 20
ns max.
This signal goes through a Xilinx XCR3256XL-10 CPLD and is delayed
by the internal CPLD logic. So the timing after going through the
CPLD r...how to set the ISP mode for programming CPLD?
chi - 2004-01-05 06:19:00
Hello,
I need to program CoolRunner CPLD using an embedded controller. How to
set the CPLD registers to work in the ISP mode?
Please explain how to do.
Regards,
Chi
...FPGA/CPLD group on LinkedIn
2008-03-02 15:59:00
FPGA/CPLD group on LinkedIn
http://www.linkedin.com/e/gis/56713/3CC3BF77FD22
Group for People Involved In the Design and Verification of FPGA's and
CPLD's to Exchange Idea's and Techniques. You should have FPGA/CPLD
Design/Verification on your Profile to Join. (The focus is more on
FP...PROBLEMS WITH COOLRUNNER XPLA3
2006-03-13 12:14:00
hi
im using digilab XCR development board which has Xilinx XCR3064
CPLD.
I/O pins in this CPLD are said to be tristate.
but when im trying to use them as tristate
its not working as one?
i mean i want one of the I/O pin to go high impedance but its not?
can any one tell me how can i make I/O ...CPLD : Generating reset signal
Valentin Tihomirov - 2003-11-18 15:58:00
Active reset is high. In passive state (nRESET) I pull signal to GND with
130k resistor. Pushing a button connects signal to 3.3vcc with 10R in
series. Signal is filtered with 0.1uF capasitor. This circuit works well in
the absence of CPLD.
After plugging power, signal is low (as expected). Pr...good starter kit
cpex - 2004-04-28 11:54:00
Hello,
I am a computer engineering student and I am looking to do a project which
will require a FPGA or CPLD. I will need something with > 70 general IO
pins. I am looking for a development board that will give me an expansion
port to plug it into my project. I want something less than $100 ...Essential hazards in CPLD's?
Preben Mikael Bohn - 2003-10-31 11:58:00
Hi NG, are essential hazards avoided in CPLD-designs?
If for example I were to design a counter with a subsequent comparator
in a CPLD, would I be sure that I got no glitches in the output from my
comparator? Or would I have to filter the output before I used it in
other part of the CPLD?
...FPGA/CPLD Design Group on LinkedIn
cpld-fpga-asic - 2008-08-27 06:22:00
FPGA/CPLD Design Group on LinkedIn
Group for People Involved In the Design and Verification of FPGA's and
CPLD's to Exchange Idea's and Techniques. You should have FPGA/CPLD
Design/Verification on your Profile to Join. (The focus is more on
FPGA/CPLD in the product as opposed to FPGA's solely ...CPLD program editing
abhi - 2005-09-29 10:08:00
Hi Group,
I need to edit a program loaded in a CPLD.I can read a JDEC file from
the CPLD.How can I convert that file into a readable program which I
can edit?
Thanks
...How to extend a pulse width without clock!
peterzhu - 2003-09-03 04:30:00
Due to a chip bug, I have to extend a pulse width(negative)from 10ns
to 100ms in CPLD(Altera 7128). But the difficult is that I have no any
clock into the CPLD, so the CPLD is pure combination logic. how to
extend it in such case?
Help me!
...How to deal with unavoidable setup time violation in CoolRunner II cpld?
2007-06-22 10:28:00
Hi,
I apologize if this question is too stupid... basically I want to
build a protocol analyzer with a CoolRunner II cpld. the CPLD will
watch the bus line and extract data. I have passed behaviorial
simulation and fitted the device. but post-fit timing simulation gives
me some setup time viola...CPLD-SPI_flash configuration system problem.
mughat - 2006-02-16 01:59:00
I have a problem width my CPLD-SPI_flash configuration system.
I have made a configuration interface for my Spartan 3 FPGA involving a CPLD
(CoolRunner 2) and SPI flash (M25P32).
My FPGA is set up to serial master configuration mode. The FPGA is
generating the clock for the CPLD and the CP...DPLL in CPLD
Jim - 2004-06-24 06:01:00
Hi all,
i need to implement a (D) PLL in a CPLD.
Purpose is to multiply a frequency of 32KHz to 4,096KHz.
On board PLL's don't work since the freq. is very low
How do i start?
Jim
...ML403 FPGA and CPLD
Marco T. - 2007-02-15 02:34:00
Hallo,
I would connect virtex-4fx and cpld to test an i2c slave peripheral.
Into virtex-4 I have programmed a small system with microblaze, opb_i2c, and
some other peripherals.
Into cpld I would program a small i2c custom slave peripheral.
Is it possible to realize, otherwise I have tro...cpld version?
2007-01-31 09:32:00
I want to order a xilinx xc9536 cpld. In one catalog I found the following
9536 XLX 44 PLCC In-system Programmable FLASH CPLD, 15ns, 100MHz
XC9536-15PC44C. 384-8980
9536 XLX 44 PLCC In-system Programmable FLASH CPLD, 10ns, 100MHz, 3.3V (IND
TEMP) XC9536XL-10PC44C 384-9016
What are the 15n...how to evaluate the needed number of gate?
Mouarf - 2004-11-25 07:05:00
hello all,
For a hobbyist purpose, I want to drive an LCD display (320x240) with a CPLD
or FPGA in a standalone device (weather station). I've already played with
FPGA and VHDL for some projects but I was never involved in the hardware
part of such projects.
The CPLD would have to read d...CPLD/FPGA with Linux
Scorpiion - 2009-10-22 12:01:00
Hi, I have just started out with some VHDL in school and would like to have
something at home to play with. I'm not sure of CPLD vs FPGA for my use,
but CPLD feel more suited for smaller projects I guess. My question is how
Linux is supported as developmentplatform? (I have linux on my computers at
...Is a CPLD appropriate for this triple PWM application?
they call me frenchy - 2005-09-13 18:35:00
I am thinking of using a lowcost CPLD as a brain to do various logic
functions in addition to driving 3 separate PWM generators. The PWM
generators will receive their intputs from a state diagram that is
cycled through via a pushbutton. Sounds simple. Does anyone object
to using a very low co...Re: S3E USB2.0 port
Antti - 2006-08-01 04:38:00
bijoy schrieb:
> Hi Antti,
>
> In Spartan3E Starter Kit can we use FX2 processor to reporgram the FPGA ?
>
> have some application like that and would like to know whether it works before trying in actual board
>
> rgds bijoy
sure the FX2 can be used to load the FPGA!
the FX2 and...Xilinx Spartan Logic Cell/Slice vs. Xilinx CPLD Macrocell
Eric - 2008-11-21 11:41:00
Hello all,
knowing that one Spartan-3-FPGA-Slice stands for 2.25 Logic Cells, how can
I convert this into a Xilinx CPLD Macrocell?
Example: Using an i2c-module with 150 Slices in a Spartan-3, which CPLD
Device (number of Macrocells) would be sufficient?
Haven't found any reference at xilinx ...PLL in CPLD
Kriki - 2004-09-16 11:46:00
I need to program a digital PLL in a CPLD.
I tryed to use an external Clock Generator @ 24.576 MHZ, but the data
signal is not exactly that frequency.
So can anyone help me with that problem ???
...could I drive Altera MAX II CPLD with LSTTL outputs?
2005-01-30 23:24:00
The MAX II can tolerate 3.3V input, I believe. I read some TTL data sheets
but they seem all provide typical VOH(3.1V) and minimal VOH(2.4V) only. The
max VOH is usually not provided. Could I drive the CPLD i/o pins directly,
with the LSTTL outputs?
I will try to use some LVTTL to interface t...which Altera CPLD?
Manfred Balik - 2005-11-07 05:56:00
I want to use an Altera CPLD to do the interface between an ISA-Bus and a
Cyclone II-FPGA.
The CPLD should satisfy the criteria of the ISA-Bus timing to enable/disable
the FPGA and do the level-conversion between the 5V ISA-Bus-levels and the
logic levels of the FPGA (3,3V or 2,5V or 1,8V).
...programming a LC5512MB using the IEEE1532 extension
Burkhard Schermer - 2004-10-14 16:32:00
Hi all,
I tried to program a Lattice CPLD LC5512MB via the Xilinx parallel cable by
using Xilinx iMPACT in batch mode with an ISC-file. The programming
perfectly worked with an empty CPLD but if the CPLD already was programmed ,
strange things was happened - all Bits was programmed with zeros...Basic jitter from a CPLD (XC7500XL)
Jim - 2004-02-25 08:06:00
This is my first design using programmable logic, so apologies if this
question can be found in the datasheet or timing report - I don't know quite
what I'm looking for.
We have a Xilinx XC9572XL (10ns) being driven by either a 12.288MHz or a
6.144MHz clock on the GCK pin. The clock has max ji...why use an FPGA when a CPLD will do ??
Matt Clement - 2006-03-03 15:11:00
Hey guys/gals
What are the advantages and disadvantages of using a CPLD instead of using
an FPGA for a design?
Thanks
...ISP for XCR3256XL
chi - 2003-12-09 06:59:00
hai,
I am new to the CPLD programming. I have to upgrade the
CPLD(XCR3256XL) program using embedded controller. How commands like
ISPEN, FERASE etc., will be called?
Can anyone explain?
Thanks in advance,
Chi
...how interfacing of cpld and cpu done?
2007-09-21 02:16:00
please give me information about inerfacing of cpld xc9572 & cpu
...