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DCM
Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.
We found 884 threads matching "dcm"
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The most relevant threads are listed first
DCM with instable clock
2007-11-22 03:19:00
In a design, I have to generate several clocks with precisely phase
relationship, I'd like to use DCM. But the clock_input is not stable.
It could possiblely change frequency, even stop for a while. I dont
have input signal to reset DCM. How can I use DCM in this condition?
Or, if don't use DCM,...
DCM ISE6.2.3 sim problem
wolfgang - 2004-07-01 09:52:00
hey guys!
i trie to simulate a dcm design with modelsim, but the dcm doesn't start. i
tried to reset the dcm after applying clkin, it seems, that the dcm is
working, but clkfx is only a amount of spikes instead of a 50:50 clock but
at the right frequency. clkin is a 60%:40% clock with 33 MHz.
...Spartan 3 DCM
maxascent - 2006-03-14 07:52:00
If am running a simulation in modelsim an there is a DCM block with a
locked signal. Now because correct me if I am wrong but I would need to
stimulate the locked signal myself because the DCM will not set it as this
is just a simulation and the DCM is a piece of hardware. Hope that makes
sense?
...DCM vs PLL
Sharan - 2009-04-01 10:01:00
Hi,
From the datasheets, it is looks like the only major difference
between DCM and PLL is that PLL additionally does jitter filtering.
Rest of the features are present in both these macros. So what decides
whether one should use a PLL or DCM in FPGA.
The following are the common features p...Problem locking a DCM driven by FX output of another DCM
MM - 2007-09-06 14:50:00
I have a design with 3 DCMs. The first DCM generates 280 MHz out of 210 MHz.
It is then divided by 2 and 4 in a PMCD. There are 2 more DCMs, one driven
by resulting 70 MHz clock and another by 140 MHz clock. Both have problem
locking. Their resets are slightly delayed and negated locked condit...Xilinx Spartan DCM jitter spectrum
Nico Coesel - 2007-03-08 17:04:00
Hello all,
Does anyone has some numbers on the frequency spectrum of the jitter
from a DCM? The datasheet says the DCM has a jitter of 100ps but I
would like to know a bit more about the spectrum to determine whether
or not the clock from a DCM is usefull for sampling.
--
Reply to nico@nc...DCM configuration in Virtex-4 FPGA
2008-04-21 08:17:00
Hi all,
I'm having a little problem to implement a DCM. It's the first time i
need it (to be able to use DDR SDRAM).
Before i'm going to think about a design for a memory controller, i
first want to verify that i'm able to control a DCM. I've read a lot
of datasheets, and think i know the the...Re: Strange ddr controller bugs.
dadabuley@gmail.com - 2008-07-14 03:56:00
Thanks all and I am already solve this problem, below is the report:
I use vertex5
The main problem happens at the reset of the IDELAYCTRL block and DCM.
the DCM generated the clk and clk_270 which is 270 degree shift of
clk.
The IDELAYCTRL controlls the IODELAY component in the DDR Controller
...DCM corner issue
seb_tech_fr - 2005-11-17 12:15:00
Hi,
Does somebody know DCM corner issues? My DCM is not running at very
high clock rate (only 107MHz), so I don't think this issue is
connected with XAPP685 application notes
(http://direct.xilinx.com/bvdocs/appnotes/xapp685.pdf)
This DCM is used with an DDR-SDRAM memory controller, and when I plac...Question about Virtex-4 DCM
2007-09-10 16:27:00
I have an application where I need to model a circuit that has two
power rails.
A Vitrex-4 has only one internal power rail, so I was thinking about
disabling the DCM to simulate a power-down.
This would be done by taking the signal that is normally used to
enable power to the rest of the c...DCM Jitter?
Clark Pope - 2004-02-14 11:49:00
I had planned to generate an ADC clock from a DCM block in my VirtexII. I'm
told the jitter on the DCM output clock is likely to degrade the ADC
performance. The ADC clock is 56 MHz. The source clock will be 8MHz so I
need 7x in the DCM.
Is the jitter really a major problem at 56MHz?
Thanks...Help: Best use of DCM in Spartan-3A?
Tool - 2007-05-30 07:42:00
For my design I must use two DCMs in series. How do I best use the CLKIN,
RST, CLKFX and the LOCKED pin of the DCM?
Should i AND togheter the CLKFX and LOCKED before connecting it to the CLKIN
of the following DCM?
I read that the CLKFX can give glitches, spikes, or other spurious movement...Timespec for DCM outputs (Spartan 3) ?
Paul Boven - 2005-07-08 14:49:00
Hi everyone,
I'm using all the four phase-out signals from a DCM (0, 90, 180 and 270
degrees offset) to each clock a single D-Flipflop.
I want these flip-flops to be placed and routed as close (delay-wise) to
the DCM outputs as possible.
But I can't figure out how to set up a constraint for...DCM
Fizzy - 2006-05-17 14:33:00
Does any buddy know How DCM work and does it require an input clock
sigal or a output signal from external oscillator can work also. Plus
how do i connect my code to the output of DCM
Thanks
...dcm clkin_divide_by_2
Matt Blanton - 2006-06-27 10:11:00
When using the dcm clkin_divide_by_2 attribute on a V2P DCM, if the clk0
output is fed into the clkfb input, will clk0 be in phase with clkin?
Matt
...Xilinx warning for DCM
srini - 2006-05-11 00:18:00
Hi,
I am using a DCM in VirtexII which takes a 20 Mhz input and generates a
60 Mhz output.
I am synthesizing using Synplify Pro and using Xilinx ISE 7.1 for PAR.
After PAR, I am getting a warning that the CLKO output from the DCM is
less than 24 MHz. I know that the min. output freq. from the...IP unnecessarily using Spartan-3 DCM?
Richard Thompson - 2005-02-25 09:19:00
I've got some Spartan-3 IP from a vendor which uses a DCM. However,
the DCM doesn't appear to be doing anything. The DCM is wired up as
follows:
1) A global clock pin on the device drives signal CLK1, which goes
into the IP block, where it connects to DCM/CLKIN . CLK1 is not used
anywhere els...virtex-II DCM phase shift problems
jack lee - 2007-01-29 04:09:00
Hi all,
Right now I'm developing a board using virtex-II FPGA, and want to
implement a function
using the DCM to offer variable(dynamic) phase shifting. I use Xilinx
ISE 8.2i, and ModelSim
SE for development. As I setup the IP cores for DCM, everything looks
fine in the PRP simulation,
exc...Trouble with Xilinx DCM - Spartan3
ghelbig - 2009-12-18 18:52:00
My apologies if this has been addressed - my web searches came up
empty.
I am using a DCM in a spartan3 to generate the internal clocks - a 1-X
clock and a 1/2-X clock.
The output of the DCM goes to a BUFG. The output of the BUFG goes to
the feedback pin of the DCM, and to the rest of the ...DCM CLK driving load problem
ekavirsrikanth@gmail.com - 2007-07-14 02:49:00
hi ,
i have a probelm while i am using the DCM for clock mutiply. i am
using single DCM for my virtex 2 pro device. i have two sub modules
and a top module. i need to use DCM in all the 3 modules (2 sub
modules and top module). so i invoked dcm and component instantiation
in all the 3 modules...Problems with phase shift dcm
2005-10-11 05:19:00
Description of the problem:
I use a spartan 3-400 FPGA. A clk_100 (100 MHz), generated by a DCM is
coming out of the FPGA and is used as an input for the phase shift DCM
(clk100_fs). This construction is made to eliminate board skew.
When I measure the clk100_fs it is not what I expect. (the pha...Xilinx Spartan 3 DCM/DFS
Tony C - 2004-08-27 15:05:00
I noticed that for Spartan 3 the DCM status does not define bit 2 any
more. In Virtex II it meant that the DFS was stopped. Does this mean
the DFS never stops? I want to use DFS mode (no CLKFB). How do I know
if I need to reset the DCM?
Thanks,
Tony
...DCM start up
Roger - 2006-12-21 18:45:00
I've got a DCM as part of a 4 byte Aurora implementation on a VII Pro.
Sometimes after JTAG configuration the DCM just won't lock (hence the
ChannelUp never happens either). Once it's decided not to work, doing the
reconfiguration again or resetting has no effect. If I then configure with
an...Editing Spartan3 DCM in FPGA(8.1.03) editor
Morten Leikvoll - 2006-04-21 03:39:00
Whenever I try to change something in a DCM, a non-reversible error appears
in DRC. All the unused pins on the DCM is somehow enabled (becomes cyan),
and the DRC complains about some pins having no driver.
Also, trying to edit diff outputs causes non-reversible problems.
I can not find any...DCM constraints
=?ISO-8859-15?Q?Benjamin_Menk=FCc?= - 2005-05-05 08:50:00
Hi,
I figured out, that I have to use Place & Route Timings, because the DCM
constraints are not even included in the synthesize timings.
How can I manipulate the automatic DCM constraints? (besides overwriting
single nets or groups with FROM-TO) Or is there never a reason to
manipulate t...Problem with DCM simulation models
=?iso-8859-1?B?R2FMYUt0SWtVc5k=?= - 2006-05-02 08:33:00
Hi all, I have the following problem:
I have a Virtex-4 Board (ML403). The Virtex-4 is ES. To use the DCM I
have to add the following line to the UCF file : CONFIG STEPPING =
"ES";
The problem is that if I do this the simulation doesn't work (the DCM
never locks).
Cheers
...Virtex4 LX DCM Minimum Input Frequency
2009-05-31 23:00:00
I am using Virtex4 FPGA at really low frequecy (150KHz). I need to
double the clock at this frequency and would like to use DCM for it.
I am not sure if the DCM in V4 LX100 can take such low frequency.
Any ideas will be great.
Thanks.
CP
...Unconnected Ports
Weddick - 2005-11-23 22:35:00
When using a xilinx DCM, I receive the following warning -
Xst:753 - ... Unconnected output port 'CLK2X' of component 'DCM'.
Is there someway to let XST know that I dont want anything connected to that
port. There is about 6 ports on the DCM that I don't intend to use.
Thanks,
Joel
...[VirtexII + DCM + newbie] problems with the clocksignals from DCM
Yttrium - 2003-11-27 13:46:00
hey, i have to use a DCM as i need multiple clocks now the problem is that
they should be de-asserted (not active) before some signal, so i need some
CE signal. i tried to solve it like this:
ddr_clkx2 ...Cascading of many stages of DCM...
Kelvin @ SG - 2004-01-25 00:58:00
Hi, group:
I am using a DCM to convert 40MHz to 36Mhz...now I need 12/4/1MHz clocks
also...
May I simply cascade a three DCMs to 36MHz (CLKDV_DIVIDE = 3/12/36) or three
DCMs using Multiply/Division (violates CLKOUT_FREQ_FX_LF_Min)?
Will two DCMs cascaded together work well? In one simulatio...DCM LOCKED as reset
2005-04-05 07:27:00
Hi,
Can DCM's LOCKED o/p signal be used as reset within FPGA?
is this scheme feasible :-
PowerON Reset acts as DCM reset.
DCM's "Locked" signal, shifted by 1 SRL16 acts as reset for all the
functionality (say FSMs) within FPGA.
*FSM has active low reset
The possible need for this scheme:...Xilinx DCM Spread Spectrum feature
Kevin Neilson - 2004-08-27 00:24:00
The Xilinx DCM was originally supposed to have a spreading feature which
would smear the output clock's spectrum to reduce EMI. There are some
inputs on the DCM, called DSS_MODE and DSSEN, I think, that are for this
feature. I wanted to use this feature recently and it seems to be
unsupported....DCM and buffers
u_stadler@yahoo.de - 2006-01-04 04:52:00
hi
I have another question about DCM's:
If I use the design wizard to generate a vhdl file for a DCM the wizard
uses all kinds of Buffers. For example it also uses a "BUFG" in the
feedback loop. CLK0 -> BUFG -> CLKFB.
Is that necessary?
Do I have to use an IBUFG for the CLKIN of a DCM if n...DCM jitter (again)
Andrew Holme - 2006-11-30 15:46:00
Target = XC3S400 Spartan 3
Tool = ISE 8.2i
If I understand correctly, the DCM does not use a PLL to multiply-up the
input frequency; it's a DLL and it generates all required frequencies/phases
by selecting outputs from a tapped delay line. I heard these taps are only
tens of picoseconds a...simulation of DCM blocks
vssumesh - 2006-04-11 07:52:00
Hi all,
I am designing a hadware which use clk and 2xclk. I am planning to
use DCm block in the V4 to get the 2x clock. But the board is not yet
available. So i thought to proceed with the post PAR test. Synthesized
the a DCM block in which clk0 is fedback to clkfb through a bufg.
generated...DCM and Clock
Fizzy - 2006-05-18 16:32:00
Hi,
Considering me a newcommer to FPGA world. I am trying to use Virtex 4FX
series for a synchronous design, meaning i will be using only one clock
for whole design. Obviously if the main clock is running at 100 MHz, i
would have software components on FPGA running at different clock speed
li...CASCADING DCM
vivek - 2004-03-02 04:40:00
Hi
I would like to take the CLK2X output of DCM and give it to the
CLKIN pin of 2(TWO) DCM'S.Is it possible to do so. Does this result in
more jitter.
regards
vivek
...Xilinx DCM LOCKED signal valid after input clock returns?
Barry Brown - 2003-11-18 18:39:00
OK, the DCM input clock goes away, and I understand the LOCKED signal is not
valid. After the input clock comes back, can you rely on the LOCKED signal
to indicate that a DCM reset pulse is needed?
And ditto that question for the STATUS(2) signal when you are using the
CLKFX output?
I'm tr...Series DCM's and total Lock Time
2007-01-19 09:34:00
Hi,
I googled around a bit but could not find the answer.
I am using Xilinx Spartan FPGA, with 2 DCM's in series to generate a
32MHz clock (50% duty cycle) from a 75MHz input. (First DCM is divide
2.5, second multiply 32 and divide 30).
The first DCM is connected to a system reset via a u...Xilinx PMCD+DCM reset question...
johnp - 2006-12-15 16:51:00
In looking at the Virtex-4 documentation for the PMCD, Xilinx shows a
simple
connection from the DCM to the PMCD. They don't show the clocking for
the
reset signal going into the PMCD even though the Xilinx doc says that
the
reset should be released synchronously to with the clock.
If the ...