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DDR
Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.
We found 877 threads matching "ddr"
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The most relevant threads are listed first
DDR FPGA Design
Mounard Le Fougueux - 2007-01-31 11:39:00
I'm planning an FPGA design that will be using SDRAM (DDR Winbond
W9425G6DH5) and NAND Flash (ST NAND018W3B2AN6E). I'm not particularly
experienced in DDR memory design and there are other issues that need my
attention other then just DDR RAM design.
I keep hearing horror stories about engi...
Addressing DDR-RAM
Thomas - 2006-09-27 10:47:00
Hello,
I've got a Xilinx Virtex 4 FPGA and would like to address the onboard
DDR-SDRAM.
I've found out that I can instantiate special DDR-IO flip flops by hand
(and found an example in the ISE-Webpack documentation).
But I'm still not sure how to address the DDR-SDRAM best, especially I
don...DDR Termination
maxascent - 2006-04-08 07:49:00
I am creating a design using a Xilinx Virtex II Pro and some DDR memory. I
downloaded the Xilinx ML361 DDR Ref design to get some tips. They have put
resistors on the appropriate tracks to VTT at both the DDR and FPGA. I was
going to put the resistor at the DDR but use the FPGAs DCI to terminate a...Minimum frequency at which ddr can operate
subint - 2006-08-02 02:55:00
Hi,
I am using a ddr(mt46v32m16fn -6) ddr and Virtex4 (lx60) fpga.
And i am using the controller generated by the MIG1.5 tool. When i run
this controller in the real hardware i am getting zeros in the result
bus(read_data_fifo_out)... Dont know where i am wrong.
I am monitored a...DDR Controller
yy - 2006-08-04 10:37:00
Hi,
I am to build a fpga system that captures data from external signals
and store it to DDR, also after the capture data must be transferred to
the PC via PCI bus via DMA or so.
So this is a CAPTURE-to-DDR DDR-to-PCI... How is this sytem
implemented?
...DDR Error : partial row address regardless
2004-12-07 23:21:00
Hi,
I use V2P70 to control DDR SDRAM (HY5DU561622CT-J) in the clock of 166MHZ. The row address of this chip if [12:0].
The strange thing is that sometimes one of ddr chip will regardless parital row address[12:9]. Then this chip size is become from 16Mb * 16 to 1Mb * 16.
What kind of wrong ...ddr with multiple users
David Ashley - 2006-09-07 15:28:00
Hi,
I have about 4 different independent things that each need to access
a ddr.
On one hand it seems I can make them all wishbone
compliant then just have a wishbone ddr interface.
Would be workable/advisable to instead just have each device
control the ddr itself, and use the ddr's own ...opb_ddr connection to DDR chips
Sylvain Munaut - 2005-02-07 16:25:00
Hello
I'm planning to do a microblaze design using external DDR memory using the opb_ddr
core. However I'd like to know if there is any constraints on how to connect
(which banks/pins ...) the DDR chip. Here I only have 1 point to point connection
of a 16 bits wide DDR.
I was planning on us...Why 166Mhz DDR?
2007-04-15 15:33:00
Hi,
I was wondering how the number 166Mhz for DDR came up? Why not say...
200MHz/250MHz DDR? I am sure there is some thought process behind
that, could someone help me walk through?
Thanks in advance !
-Rohit
...Simulation problem for the DDR controller
subint - 2006-07-06 06:17:00
Hi,
I am using the DDR controller(generated by MIG1.5) for the ddr
MT46V32M16 -6 for the board V4MBlx60. I am getting the expected result
in simulation with the hdl code generated by the MIG.But when i tried
to simulate the post-par model of the code all interfaces to the ddr
are driven with ...Simulating PLB DDR in EDK 7.1 SP2 using ModelSim 6.0a
Nju Njoroge - 2005-11-23 03:08:00
Hello,
Is there an existing flow for simulating PLB DDR in ModelSim using EDK
7.1 SP2 in a full system (PPCs, pcores,etc)? The instructions are being
stored in BRAMs, as to avoid DDR initialization hassles. I have been
simulating the data-only DDR using BRAMs, however, to get a more
accurate ...Driving PLL from general I/O in Altera Cyclone
nfirtaps - 2007-03-08 14:58:00
I am trying to deserialize a DDR signal in my Cyclone. For reasons I
won't go into the DDR clock comes in off a general purpose I/O pin. I
need a way of deserializing this signal, and want to increase the
frequency of the DDR clock by 2 so I can use rising edge flip-flops.
1.) Can I somehow ...ML402 card (video starter kit) : Read/write on the ddr
hammouda - 2007-06-20 12:35:00
Hello everybody,
I am trying to make a software video processing with the VSK. For this, I want read video data from the DDR, applied the convolution algorithm and write the modified video data in the ddr. but I have some probleme to read/write in the ddr. Can anyone tell me how we can read and w...DDR Controller Blue
Digital Mike - 2007-05-21 23:49:00
Dear all,
I am working on a DDR controller that stores captured video frames
from which a VGA controller retrieves data. It (DDR controller) works
fine for the first few frames but seems dead afterward. I wonder if
anyone experienced similar problem. What I did (for initial testing
purpose) i...ML402 DDR SDRAM
Jered - 2005-11-07 15:11:00
Has anyone been able to get the ML402's DDR SDRAM running with a
MIG-generated DDR controller, as opposed to the EDK PLB DDR controller?
Xilinx is unable to confirm this works... there's a thread in this
group from July with some ML401 MIG questions, but no resolution. My
group is interested i...PLB Master writing to DDR Ram
gruve5112 - 2009-10-13 21:15:00
Hello,
Environment: Virtex II Pro/ Xilinx 9.1i
I'm trying to use PLB Master to write on the DDR Ram. I made a C program
to make the video frame buffer to read from DDR Ram 0x00000000. Now, I need
to make an IP to write on DDR Ram to output something on the video output.
I made PLB Master IP t...ML310 xirtex II pro development board: HOW TO WRITE onto the DDR DIMM?
ViKi - 2005-04-08 15:39:00
Hi,
I am trying to work with ML310 virtex II pro development board and I have
pretty much stuck with the basic stuff, Can someone please tell me:
1- How many way one can load an image into the DDR DIMM? is this correct
that all accesses to the external memory (the DDR DIMM) have to go through
...SDRAM controller selection
pinku - 2006-03-16 13:06:00
Hello grps,
Can you tell me what is the basis for selecting the DDR controller? For
example i have a micron DDR SDRAM and i have to see if it compatible
with the DDR controller which is within network processor. Wht all
parameter should i check?
Please let me know that
Regards
Praveen
...Xilinx EDK 8.1 DDR controller behavior
Antti - 2006-04-24 03:09:00
Hi
does anyone know what should happen on read access to DDR
memory space when external connections to DDR memory
are not correct? I am troubleshooting a custom board and
what I see is that OPB DDR controller makes total OPB bus
freeze on first DDR read access. ToutSup=1 and then nothing
hap...how to speed up the program running in ddr sdram
Athena - 2006-01-09 10:02:00
Hi all,
At present, I am using Xilinx SPARTAN XC3S1500 FPGA with Micro MT46V16M16 to do some projects. As my programme is very large, there is not enough space to put them in the bram, so I have to put them in the ddr sdram. However, I found that when the programme is in the ddr sdram, the speed ...Spartan3 interface with DDR SDRAM
FP - 2008-06-05 10:24:00
I would like some suggestions on interfacing the Xilinx Spartan3
device with a DDR SDRAM. The idea is to build a controller that will
set up the DDR-SDRAM so that I can do a burst read of a page of data
into a block of internal SRAM (dual port).
Your help is appreciated
...DDR-ram interface (xapp200)
Michael Chan - 2003-08-09 09:24:00
Hi,
I'm working on a University project that requires ddr-ram interfaced to a
Vertex-EM device. I am basing my design off xapp200 from xilinx. The
design uses DLLs to deskew the system clock and ddr-ram clock. The signal
fed back to the DLLs (sys_clk_fb) is apparently the ddr clk. What I d...PowerPC_DDR
2007-05-12 07:05:00
I am trying to interface a PowerPC in a Virtex-II Pro device with an external DDR memory on the board. I am using the following fucntions to read an write to the memory:
//write num. 300 to position 0 in //the DDR XGpio_mSetDataReg(0, 1, 300); //read position 0 in the DDR = ReadFromGPInput(0);
...memory
bhb - 2003-11-25 12:25:00
Hi,
I'm looking for a VHDL example code to implement a DDR memory in a Altera
'Stratix'.
(not a controler), with use of RAS, CAS, etc...
There is many example of memory in Megawizard of Quartus (DP-RAM, FIFO), but
I can't find DDR.
I would like to have this DDR include in specific memory b...Ddr sdram feedback pin
Pablo - 2007-05-24 07:08:00
Hi everyone, I want to design a model with my Smt338. This is a
Sundance board with a Virtex IIPro30 ff896-6 and a Micron MT46V16M16
as DDR memory. First of all I need to implement the hardware
architecture, so I use edk 8.1 (or edk 8.2) to create a model with
PowerPC and this DDR memory. In the...Xilinx Virtex4 DDR clock output
Brad Smallridge - 2006-10-24 01:11:00
How do you set up a differential DDR output clock?
In the Spartans there was a DDR register where you
would tie one data to 1 and the other to 0 at the
output pin flipflop.
The Virtex4 has OSERDES modules, do I use them?
Brad Smallridge
aivision
...PicoBlaze and DDR Ram
karrelsj - 2006-06-26 11:53:00
Hello.
I just started looking at Picoblaze. Has anyone completed a Picoblaze
and DDR RAM implementation? Or does anyone have any strong opinions on
this issue. My main goal is to store program data on RAM and access it
with Picoblaze. I see OpenCores has a DDR/SDRAM controller...
Thanks ...OpenRISC + DDR
karrelsj - 2006-08-21 14:23:00
Has anyone hooked in a DDR controller into OpenRISC? Anyone have any
comments or suggestions for this task? I have OpenRISC in a running
state with onchip RAM on a XUPV2P board, and now am just getting into
integrating in an external DDR RAM controller.
Thanks
...xilinx spartan3e kit ddr sdram
emu - 2007-06-12 13:10:00
Hi all,
is there any open source DDR SDRAM controller IP available (VHDL) for
the DDR SDRAM on this kit ?
...Finding DDR SDRAM SODIMM(200 pin) socket.
SeungHeun, Lee - 2005-02-04 04:17:00
Hello,
To interfacing DDR memory module to memory controller, I'm finding DDR
SDRAM SODIMM socket. (Not memory module). I tried to search serveral socket
& connector vendors like MOLEX, AMP. , but only SDRAM SODIMM and DDR DIMM
are available in their catalog.
Does anyone know the vendor and...DDR Address
yy - 2006-10-13 14:22:00
Hi,
Is it ok not to connect at least one DDR Address signal to a ddr
controller? If so, should i connect it to GND or VCCIO? Thanks.
...DDR desing with FPGA
Antti Lukats - 2005-06-09 01:59:00
Hi
I hope someone has more experience and can give advice -
what I need (for urgent customer design) is simple? design with FPGA having
high speed video memory (must be implemented with standard cheap devices
like DDR) - the constraints are both PCB size and power consumption. The
system mu...Cannot use ML310 DDR
king_azman - 2006-02-21 22:04:00
hi,
i'm trying to work with the ddr sdram on the ml310 development board. i
tried creating a simple base system with the ddr using the bsb wizard.
i also changed the ucf file as in the sample file provided. however, i
keep getting 'memory test - failed" when running the generated memory
test...DDR for Spartan 3
maxascent - 2006-03-09 06:18:00
Hi
I would like to design a DDR controller for a Spartan 3. I have tried
using MIG 1.5 but without much success. It claims to work with all Spartan
3 devices, yet I have found it to be unreliable and not generate designs
with all Spartan 3 devices. Can I ask how others go about with DDR. Do you
d...Spartan 3E starter kit DDR SDRAM
fpgauser - 2007-08-02 18:53:00
I am relying to the older "Spartan 3E starter kit DDR SDRAM code
Options" thread.
Is there such a demo out, mentioned in the thread?
I read in several groups that it is a problem to get this DDR Ram
running ?
...Measuring DDR SDRAM
2005-06-07 08:56:00
Hi,
maybe someone has had any experience on the following problem:
I am searching for guidelines on measuring data lines, strobe lines,
control lines
between DDR SDRAM and user FPGAs (DDR SDRAM controller) on the board
but unfortunately I have not found such information yet.
I would like...Usage of DDR IOBs
Venkat - 2006-07-31 22:44:00
Hello all,
I intend the demultiplex the data coming to the FPGA on dual-edge clock
using the DDR Input Buffers. However I could not find an appropriate
explanation of instantiating the DDR Input buffer for this purpose. I
am using the DCM to generate the CLK0 and CLK180 using the data
reference...Re: DDR DIMM clock distribution
Brian Drummond - 2007-10-10 09:07:00
On Tue, 9 Oct 2007 18:04:12 +0200, pgw
wrote:
> Hi
>
> I'm using Cyclone II EP2C8 in PQFP208 package and DDR DIMM.
> And I'm wondering how to distribute clock signal.
> DIMM has 6 clock signals (3 differential pairs).
> I figure out two solution:
>
> 1. Use differential output PLL_OU...Spartan 3E Starter Kit DDR RAM
maxbatley - 2007-11-08 11:41:00
Hi All,
I've got the Spartan 3E-500 starter kit from Digilent and need to use
the DDR ram on the board. I've searched this group and found lots of
references to a port of the opencores DDR controller, which has been
ported to this board, but after (a lot of) google searching I can't
find anythi...I could run my program at DDR Sdram.
Pablo - 2008-03-06 07:40:00
Hi, I have written already about this topic. At finally I have
configured a DDR SDRAM core for PowerPC so I could read and write from/
to DDR. It supports words, half words and bytes. I have probed it with
Xilinx TestMemory and Mwr/Mrd in xmdstub. Everything works fine and I
could use this memor...