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Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.
We found 1182 threads matching "dsp"
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Altera DSP Builder
DC - 2007-02-01 03:13:00
Hi guys,
Seems like Altera's DSP Builder has undergo a lot of improvements over
the past year or so. Trying to connect with other DSP Builder
aficionados and to promote more discussion on DSP Builder in general,
I have created a google group altera_dspbuilder. There, we can help
each other ou...
A Way for a DSP to tell an FPGA to load itself from Flash
axr0284 - 2007-07-09 13:21:00
Hi,
my setup is as follows:
1) DSP ADSP-21065L
2) Xilinx xc3s250
3) Intel JS2BF320J3D Flash
I am able to have the DSP load itself from flash but after it's done
loading, I would like the DSP to tell the FPGA to load itself from the
same flash. They will be sharing address and data lines an...TI DSP soft core in Xilinx?
cpope - 2007-11-15 19:30:00
I have a V4FX based product and I'd like to have a DSP coprocessor to go
with the the powerpc that handles my operating system. Are there TI c54x or
c3x soft cores out there that could be compiled into a xilinx fpga? Could be
anyone's dsp, I suppose, so long as it has a large existing code base a...Xilinx Spartan 3A/DSP with Coregen 9.2i?
talkb - 2008-01-27 01:16:00
I thought about buying the Xilinx Spartan3A/1800DSP starter kit ($295 USD.)
When I ran Core Generator 9.2i.04 (with IP Update #2), created a new
Spartan3A/DSP project, then looked at what wonderous DSP-blocks I could add,
I discovered almost everything fun is greyed out.
Basically, the IP-Core...AHDL Abandoned in Quartus?
jjlindula@hotmail.com - 2005-08-15 14:58:00
Hello, last year there was a post concerning Altera abandoning AHDL in
their new tools, such as Quartus. The post also said that you
couldn't use AHDL with SOPC Builder or DSP Builder. If this is true,
it seems to be a big constraint for the designer; then again, I have
yet to use SOPC or DSP Bu...1.8V LVDS on spartan3A DSP
Guru - 2009-11-11 12:27:00
Hello everybody,
I am developing a camera with a Spartan3A DSP and a sensor which uses
1.8V LVDS. The Spartan 3A DSP datasheet says that only 2.5 and 3.3V
LVDS is supported. The signal rate is 108MHz DDR.
Any suggestions what should I do? Specify in UCF LVDS_25 and pray to
work OK?
It is p...DSP soft processors
2006-01-11 22:08:00
Hi folks,
are there any DSP soft processor cores for fpgas available. I have done
a search and only found 32 bit RISCs but no DSP processor cores.
Thanks in advance
Sudhir
...Can the complex DSP archetecture based on FPGA+DSP be replaced by FPGA
zhj1985 - 2009-03-24 10:11:00
Generally, the most popular DSP archetecture which focused on complex
digital signal processing is based on DSP +FPGA. FPGA is often used as a
coprocessor for a DSP because those PowerPC 440 cores aren't as fast as DSP
and those algorithms which are developed by C language can be developped
more eas...how to choose the FPGA/DSP coprocessor system architecture
2009-05-13 16:54:00
Dear All:
I am thinking about my system, the picture is here:
http://www.flickr.com/photos/26914086@N05/3528643109/sizes/l/
I want to transfer the raw/processed image sensor data to USB 2.0 or
dpram.
Two choices:
1. ADC -> DSP, this means parallel ADC, then DSP processed data ->
U...Virtex 5 DSP.
2008-10-21 21:43:00
Hi, Im new to DSP stuff and have a very simple question.
Since the multiplier in virtex 5 dsp is 2's complement ... does that
mean when using the std_logic_unsigned library, the maximum number of
bits A input can have is 24 instead of 25 and 17 instead of 18 for B
input?
Whereas I can use 2...DSP
SaHiD - 2006-02-21 05:45:00
Please Give me outline of doing a project of dsp processor design.
...Altera DDR SDRAM & external DSP
Jerry - 2004-09-07 20:53:00
The question is "Has anyone successfully integrated two DDR SDRAM
controllers controlling one block of ram?"
The alternate approach is to use the DSP HPI port as the transfer port
between the shared SDRAM and the DSP. This would
not rely on using the DSP DDR SDRAM controller to access the sha...Spartan3 initialization with DSP
Marco - 2006-01-17 11:46:00
Hi, I have to initialize a Spartan3 with a Blackfin DSP. I was thinking
to connect the CCLK and DIN pins to the serial port of the DSP (SPORT),
but while the DIN is dual-purpose, the CCLK is dedicated. I'll then
need, when all properly configured, FPGA and DSP to communicate with
the SPORT once ...Multiply Accumulate FPGA/DSP
bart - 2005-05-03 14:04:00
I have been tasked with trying to implement a FFT algorithm in a
FPGA/DSP architecture. The algorithm would be a N point FFT with 1000
frequency bins. Each frequency bin would require a multiply, by the
constant e^jx, and then accumulate every 1 microsecond. This turns out
to be 1000 multiply...FPGA/DSP system design problem
2009-05-13 17:13:00
Dear All:
I am thinking about my system, the picture is here:
http://www.flickr.com/photos/26914086@N05/3528643109/sizes/l/
I want to transfer the raw/processed image sensor data to USB 2.0 or
dpram.
Two choices:
1. ADC -> DSP, this means parallel ADC, then DSP processed data ->
U...PDSPs vs FPGAs for DSP
Orbit - 2004-09-05 09:52:00
Hi,
I am reading Uwe Meter-Baese's book "DSP with FPGAs" and am trying to gain
some perspective here. FWIW, I develop embedded apps on the Atmel 8 bit AVR
platform with CodeVision C compiler.
What are the pros and cons of going PDSPs vs. FPGAs to implement DSP for my
8 bit apps?
This boo...DSP designs that exceed provided embedded arithmetic hardware
Ken - 2005-03-23 11:41:00
Hi folks,
This question is aimed at those who have created designs including DSP using
a device family containing dedicated arithmetic silicon (e.g. Xilinx
DSP48/18x18s/Altera DSP blocks):
On what % of designs you have completed did you run out of dedicated
arithmetic blocks and have to ...image processing on SPARTAN-3 DSP TRAINER MODEL : MXS3FK-DSP
sagarvetal - 2011-02-24 08:28:00
hello...
i want to do image processing on SPARTAN-3 DSP TRAINER MODEL :
MXS3FK-DSP
fpga. i am using xilinx system generator software to build the logic.
i am not able to find the way how to store the .bmp image on the above
fpga.
and how to interface the stored image with the logic built o...Re: VHDL or verilog
2006-02-16 18:01:00
Have you tried DSP with FPGA by Meyer. That gives a good introduction
in VHDL DSP design.
Paul
...[ANN] DSP for FPGAs 4-Day Course
Ken - 2004-05-04 05:54:00
Just to let you know we have a DSP for FPGAs
course running on 24th-27th May. Info and
details at:
http://www.sli-institute.ac.uk/fpgacourse
...Using DSP Builder with Quartus
jjlindula@hotmail.com - 2005-03-16 14:47:00
Hello, I've been hearing a lot about DSP Builder and was curious if it
is worth learning? Can anyone share their experience pros/cons? Are
they any good references I could pick and teach myself?
Thanks,
joe
...DSP Ip Core
Jean-sébastien LEROY - 2008-02-29 03:33:00
Hello all,
I am looking for a free DSP Ip core (like the OpenCores C54).
Have you some idea to look for ?
Best regards,
JSL
...system generator from Xilinx
2007-01-21 13:32:00
Hello all,
I just wanted to find out how good system generator software is? I can
program in VHDL and would like to know if the SYS gen software would
make life easier for me when it comes to designing DSP filters , FFTS
or other DSP blocks.
Does Xilinx provide IPs separately for the DSP block...DSP with sensor i2c interface
Gladys - 2010-07-30 04:47:00
Hi all,
I have to interface DSP with 3 image sensor,s there're only two i2c
GPIO for DSP, so I need to implement an i2c core in FPGA, I've
implemented an i2c slave core to receive data from DSP and store them
with a large LUT in my FPGA and another i2c master core in FPGA to
send the stored i..."DSP Dev kit stratix II edition" Vs "ML401 Evaluation platform"
spartan - 2005-02-23 16:22:00
Hi,
I want to buy a development kit that has a strong processor and also DSP.
I've found "DSP Development kit, Stratix II edition" from Altera and
"ML401 evaluation platform" from Xilinx. Does anyone have experience in
using them? if so which one is more reliable?
Thanks a lot.
...Connecting ADC chip to sparta 3 a dsp
lakshmi3489 - 2010-02-01 07:32:00
hi there
I have an ADC chip which is working in the LVDS mode.
The data out(D0+,D0-,......D13+ and D13-),along with data clock
out(DC0+,DC0-)
and out of range(OUR) are connected physically to Sparta 3a dsp.
My question is how do I directly collect these LVDS signals in my sparta
3a dsp ...Input pins that are driven but not used
Tom Derham - 2003-10-27 13:08:00
I have a DSP chip with address/data bus and control pins interfaced to a
Spartan IIE.
The DSP is driving these lines, but I do not ever need to use some of them
in my FPGA design.
What should be done with these input pins? At the moment they are
completely unassigned (using Webpack). Some are...DSP or FPGA for high-speed image processing?
kyori - 2006-12-16 23:15:00
Hi,
I am going to start a project of onboard high-speed CMOS image
processing.
I am goint to perform certain *block matching algorithm* or *Fourier
Transform* between successive frames and the fps would be 1000 or
more..
The interface between the CMOS camera and the board is standord
Ca...Mistake in Xilinx dsp-book.pdf?
Holger Blum - 2006-01-14 17:00:00
Hello!
While working with a MAC-FIR I came across an equation in Xilinx'
DSP-book (http://www.xilinx.com/publications/books/dsp/dsp-book.pdf)
which seems to be wrong in my eyes.
On page 65 equation 4.4 for the generic saturation level says
Output width = ceil(log2(2^(b-1)*2^(c-1)*N))+1
Whe...TI DSP + Virtex-5 using EMIF interface
techG - 2008-06-09 05:24:00
Hi all,
I'm working on a realtime application that requires to elaborate a
digital video stream 25fps. Algorithms are very time consuming and an
hardware parallel solution can help to satisfy time constraints.
Finally I decided for a mixed SW and HW that consists in a TI DSP and
a Virtex-5 co...Spartan3 bus for DSP
Marco - 2005-11-07 08:08:00
How could I implement a bus in my Spartan3 to let it communicate
thorough a 16bit wide, 100MHz bus with a Blackfin DSP? Thanks, Marco
...Re: V.34 Modem IP core
2007-03-05 01:00:00
"GX" writes:
> any IP vendor out there who supply hard/soft core for V.34 Modem?
V.34 is normally (probably always) implemented in software. You could
put any DSP core (or RISC core with DSP capability) into your FPGA or
ASIC, and run a V.34 implementation on it.
...Exciting Project!
2006-07-14 19:16:00
Crystal Instruments is an engineering firm, founded in 1996 and focused
in the area of embedded systems, digital signal processing (DSP) and
Windows programming. With over eight years' experience creating
embedded and DSP systems for product evaluation, algorithm
implementation and fine tuning f...[Promo] Danville releases SHARC kit for $199
Al Clark - 2005-03-02 15:08:00
Analog Devices, Altera and Danville Signal joined forces to create the
ADDS-21261/Cyclone DSP & FPGA Evaluation Package featuring Danville's new
dspstak 21261zx DSP Engine and dspstak c96k46 I/O Module.
The dspstak 21261zx combines the power of a SHARC DSP and a Cyclone FPGA.
With a support...Re: spartan 3 vs virtex 2
Benjamin Menküc - 2005-02-28 04:01:00
Hi,
I think the virtex-2 still has a faster clock, besides that I think you are
right. Maybe some special DSP implementations need more gates on the
Spartan, because it doesnt have as much special DSP functionality...
regards,
Ben
...DSP/FPGA/video board?
Georgi Beloev - 2004-08-23 17:51:00
Hi,
I'm looking for an inexpensive (up to $1000) development board with the
following features:
- Relatively fast DSP, e.g., Blackfin.
- Mid-range Cyclone II or Spartan-3 FPGA.
- At least 4 MB SDRAM.
- Video in (CVBS and Y/C), digital video decoder.
- Video out (CVBS and Y/C), digital vi...System Generator Xilinx ML403
eric - 2008-06-26 10:58:00
Is it possible to use the System Generator for DSP with the ML403 with
GigabitEthernet or USB? They only support ML402 directly, why?
Has anybody a BSB and sources how to manage it to use ML403 for DSP
with Matlab programs?
Thx
Eric
...DSP vs FPGA
2005-11-30 07:33:00
Hi every one,
It seems that implementation of DSP algorithm In simulink is possible
not only for TI DSPs
but also XILINX FPGAs.
I intend to implement a baseband 64 QAM modem with MATLAB/SIMULINK.
It should be added that the bandwidth of afforementioned modem is 8 KHz
and about 64 Kbps.
...Video - DSP Eval board with Altera
homoalteraiensis - 2006-08-14 08:52:00
Is there anybody out having experiences with an evaluation board,
containing an Altera FPGA like Cyclone or Stratix and doing Video
processing with it?
Can anybody recoomend a certain board with a good analog behaviour
(high dynamic ADC) - possibly with a (hard) DSP?
Thanks in advance.
...Quartus DSP Blocks
rnbrady - 2006-10-26 03:04:00
Hi
I'm compiling my design using Quartus II and using a Cylclone II EP2C35
device. The fitter reports currently says it's using 34 /70 embedded
9-bit multiplier blocks. I'd like to see how much extra logic it uses
if I tell it not to use the embedded multipliers, but I can't seem to
turn the...