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LVDS


Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.

We found 387 threads matching "lvds"

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The most relevant threads are listed first

LVDS pin assignment

=?ISO-8859-15?Q?Benjamin_Menk=FCc?= - 2005-04-20 14:55:00
Hi, I am designing the following converter: LVDS -> some processing -> LVDS. Each LVDS Interface has 3 channels and 1 clock channel at about 300 MHz (differential clock rate). My question is if I should use GLCK pins for the incoming LVDS clock? Should I also use GLCK pins for the out...LVDS pin assignment

LVDS Receiver in FPGA

woko - 2008-09-07 07:38:00
Hi FPGA specialist, we are would like to know if it is currently possible to implement high speed LVDS receiver or transmitter in FPGAs. Our next gerneration PCB board would have about 12 LVDS receiver (SN65LV1224B) , 6 LVDS transmitter (SN65LV1023A) and an FPGA onboard. Please note that ...LVDS Receiver in FPGA

Lattice / M-LVDS

Metin - 2007-02-16 04:14:00
Hi there, I've heard that some Lattice FPGAs support M-LVDS signalling. Did anyone has any experience with lattice M-LVDS? Are they true M-LVDS driver/receivers? What are the deviations from the TIA/EIA-899 specification? Finally are They current-mode drivers? Thanks. ...Lattice / M-LVDS

regarding changing serial data out to LVDS form

ekavirsrikanth@gmail.com - 2006-11-13 05:32:00
hi all, i have serial data out in my design and i need to convert it to LVDS signal how can i covert it to LVDS . my end system needs differential data as input so i need to convert to LVDS. i have written code in vhdl and data out is ready which is serial data . i am using spartan 3e fpg...regarding changing serial data out to LVDS form

Using LVDS in Lattice ECP3

PGS - 2009-03-27 10:46:00
We need a quick guide about how to instantiate a LVDS input and a LVDS output on the ECP3. Using the VHDL language (and Symplicity), we would like to use a set of LVDS-inputs (say AN and AP on the pins, and AQ leading into FPGA). I would expect, that I could instantiate a LVDS-input-cell by na...Using LVDS in Lattice ECP3

LVDS via Emulation

Netoko Young - 2007-07-04 14:10:00
Hi all, I've just read something about LVDS via emulation, in the datasheet of the FPGA its specified that some banks natively support LVDS while some other banks are specified to support LVDS in emulation only, does this mean that to support LVDS an external resistor is needed? Thanks, N...LVDS via Emulation

max lvds IO speed on V2Pro

sjulhes - 2006-04-05 01:53:00
Hi, We have to interface a V2Pro with a DSP's communication ports which have LVDS links up to 500Mhz ( taken from datasheet ). We have some experience on V2Pro LVDS I/O but at slow speed and we are wondering what speed we will be able to reach with this LVDS DSP link. DSP and FPGA are on ...max lvds IO speed on V2Pro

Re: LVDS output pins of Altera Cyclone II

onlyspam@online.ms - 2006-12-02 14:32:00
I'm trying to use a FPGA to control a flat panel display that has LVDS inputs. Displays try to draw current from active LVDS lines if the power supply of the panel is switched off. That is very harmful for the TFT and sooner or later it gets destroyed. That is why I have to tri-state the LV...Re: LVDS output pins of Altera Cyclone II

drive LVDS clocks with a spartan3

Julien Lochen - 2006-11-09 04:31:00
Hello, I work as Design Engineer at Bull SAS in France (Server Design and Development). I saw a webcase on the web in which someone try to provide some guidance concerning LVDS signals. I am not sure to have understood all your answers, so please let me ask the following question : I am ...drive LVDS clocks with a spartan3

Re: Spartan 3e, LVDS LCD.

2008-08-10 10:38:00
> I've acquired a spartan 3e starter board, and have completed some of the > simpler tasks on fpga4fun.com. I am looking for some guidance on how > to implement LVDS to control a LCD panel. > I have the docs on the panel, it is a 1366 x 768 40" LCD from a tv. It > uses 4 lvds pairs @ 80 m...Re: Spartan 3e, LVDS LCD.

LVDS on Spartan 3

Chris Cheung - 2004-02-13 15:25:00
hi all, I am new to the LVDS stuff. I am going to implement a LVDS transceiver on XC3S400. I got the XAPP622 application note (talk about using LVDS on VirtexII and VirtexII pro) from Xilinx sites. I am wondering if the same idea could apply to Spartan 3 (I know Spartan 3 runs slow than...LVDS on Spartan 3

LVDS on Drigmorn1

John Adair - 2007-12-15 17:43:00
In answer to all of you who asked about LVDS support on Drigmorn1 we believe 2 pairs of LVDS are very viable but as yet have not tested the feature. Some others may be possible but pin routing is not so good. John Adair Hone of Drigmorn1. The low cost starter FPGA development board. ...LVDS on Drigmorn1

Spartan-3 LVDS driving TFT LCD panel..?

Mike Harrison - 2005-08-31 15:04:00
Does anyone know how feasible it is to drive a TFT panel LVDS interface (sometimes called Panel-link I think) direct from the S3 I/Os ? If so, what sort of frequency can you get up to - I saw a mention recently about using the DDR registers to reduce the data rate but couldn't immediately see any ...Spartan-3 LVDS driving TFT LCD panel..?

Re: LVDS output pins of Altera Cyclone II

onlyspam@online.ms - 2006-12-01 14:32:00
Hi Rob, I know that I have to use the assigment editor to change the output type from LVTTL (default) to LVDS. But when using LVTTL I always have access to the "output enable" of the output pin to tri- state the pin. But this does not work when using LVDS output. The output register is ...Re: LVDS output pins of Altera Cyclone II

1.8V LVDS on spartan3A DSP

Guru - 2009-11-11 12:27:00
Hello everybody, I am developing a camera with a Spartan3A DSP and a sensor which uses 1.8V LVDS. The Spartan 3A DSP datasheet says that only 2.5 and 3.3V LVDS is supported. The signal rate is 108MHz DDR. Any suggestions what should I do? Specify in UCF LVDS_25 and pray to work OK? It is p...1.8V LVDS on spartan3A DSP

Can Spartan-6 Support M-LVDS ?

ajpanicker - 2010-04-09 10:01:00
Does the Spartan-6 LX family or Spartan3A support the Multipoint-LVDS specifications? We need input and ouput buffers compliant to M-LVDS type1 and types 2. Also , the buffers should be 5V LVTTL tolerant. ...Can Spartan-6 Support M-LVDS ?

help with Xilinx LVDS syntax

Morgan - 2006-12-06 12:02:00
I apologize if this questions has been answered already. I was unable to find an answer in my search through this group. If you have any experience using LVDS with Xilinx FPGAs, please help. Q: If I have a LVDS input, must my top-level entity specify both the N and P ports, or is there a wa...help with Xilinx LVDS syntax

Interfacing Cyclone III to 3.3v LVDS devices

liqiyue@gmail.com - 2007-11-28 22:46:00
How can i interface the cyclone III with 2.5v LVDS to 3.3v LVDS adc & dac ? Thanks ...Interfacing Cyclone III to 3.3v LVDS devices

LVDS in Cyclone-II

John_H - 2006-04-05 13:46:00
Hello folks, I may be starting my first Altera design in a few years but I was disappointed to find that the Cyclone-II LVDS drivers aren't true differential drives: an external resistor network is needed to produce proper LVDS levels like in the "old days." Does anyone here have experie...LVDS in Cyclone-II

LVDS for lcd panel and RocketIO

=?ISO-8859-15?Q?Benjamin_Menk=FCc?= - 2005-04-10 16:21:00
Hi, I want to connect a LCD Panel with LVDS to my Virtex2Pro. The LVDS frequency is max 80 MHz. My fpga runs at 100 MHz and is speed grade -5. Do I have to get into the RocketIO stuff now, or does it have nothing to do with it? regards, Benjamin ...LVDS for lcd panel and RocketIO

Need support for LVDS to Tmds translation on altera device

morp - 2009-08-22 18:05:00
Hi, I've been wondering how to translate lvds drive to tmds, my application is chip to chip only, i.e tmds does not go through any cable etc. From altera fpga, the lvds (translated into tmds) goes to a tmds input chip. What could be a solution for this? thanks. ...Need support for LVDS to Tmds translation on altera device

Chip to Chip LVDS

yy - 2006-11-06 19:55:00
Hi i'm currently working on a high-speed chip-to-chip serial interface FPGA interface, i would like to know some suggestions regarding FPGA differential signalling; especially the trace matching of pair of LVDS signal, and the whole Channel (set of LVDS signals; Tx_Frame, Tx_Clk, Tx_Data) etc. ...Chip to Chip LVDS

Maximum LVDS-rate of Spartan 3E

Thomas Entner - 2005-03-11 16:09:00
Does anybody know the maximum LVDS-rate of Spartan 3E? I did not find anything in the datasheets, while the Spartan-3 datasheets says 622 Mb/s IO transfer-rate (I think this is valid for LVDS). As we know our friends at X & A, when a nice high number gets quietly removed from the feature-li...Maximum LVDS-rate of Spartan 3E

Xilinx Virtex II fpga - providing single ended signal to lvds defined pin

TD - 2005-09-01 12:18:00
Hello, I am having ADI board containing xilinx virtex II chip. There are two pins defined as LVDS_33 I/O but I wanted to reprogram them as single ended signals and hence I had removed the 100ohm resistance between the lvds signals. The lvds receiver output signals are ignored by my design. Hence...Xilinx Virtex II fpga - providing single ended signal to lvds defined pin

electrical interface problem LVPECL - LVDS multi-inputs

Kurt Kaiser - 2006-12-13 05:17:00
Hi there, I'm currently having a serious problem: I got an LVPECL clock synthesizer and I want to connect it to several clock inputs on my FPGA. The FPGA features 2 LVDS interfaces, whereas each LVDS pair is located at opposite sides of the device, meaning there will be some extensive routi...electrical interface problem LVPECL - LVDS multi-inputs

Starting with LVDS

Frank Schreiber - 2006-01-22 12:29:00
Dear all I'm starting with LVDS. My task is sending 8-bits signal to LVDS Transmitter port on my board. I declared a 8 bits vector, assigned pins, and changed values in 8-bits signal, but nothing happended in my oscilloscope. Assume that pins-out are right assigned, all wires and DAC are workin...Starting with LVDS

LVDS output pins of Altera Cyclone II

onlyspam@online.ms - 2006-11-30 17:05:00
Hi, does anybody know how to switch of the LVDS output pins of a Cyclone II? I use the "alt_lvds" megafunction but there are no inputs to this megafuction to enable or disable the LVDS output pins. I thought about writing my own serializer as a workaround but I have no idea how this i...LVDS output pins of Altera Cyclone II

LVDS i/o in a SystemVerilog Interface block

fpgabuilder - 2010-03-01 20:28:00
I need to instantiate LVDS interfaces in my top-level. I am planning to use SV interface blocks. Altera's documentation suggests that LVDS i/os should only be instantiated using a megafunction. But the interface blocks do not allow hierarchy so I cannot instantiate a megafunction inside the i...LVDS i/o in a SystemVerilog Interface block

Using SelectIO LVDS to drive 40 inch backplane trace

Goli - 2009-03-24 02:16:00
Hi, I am designing a system which needs multiple interfaces (about 16) to backplane running at about ~700Mhz. These are going to be source synchronous interfaces and clock will be available. I did not wanted to use the build in transceivers because the 20 transceiver devices are very expensi...Using SelectIO LVDS to drive 40 inch backplane trace

Lvds input problem urgent

Dan - 2005-04-29 09:42:00
I have 2 signals that come from an lvds transmitter sources: lvds1p, lvds1n. I use an cyclone EP1C6. I want to put these signals on pins 124 and 123. how can i make this and how a can use after that this signal in my design (transmitter -> lvds1p,lvds1n -> fpga:receive these signals -> ...Lvds input problem urgent

LVDS in Xilinx (Spartan-3)

Jason Daughenbaugh - 2003-09-19 18:21:00
Hello all, I am considering using the LVDS mode in spartan-3 FPGAs to run offboard via a cat-5 RJ-45 connector. We have been doing this for a long time with LVDS parts from TI and National, but using the FPGA directly would be a cost savings (but also require a lot of pins!) I am concerned...LVDS in Xilinx (Spartan-3)

Xilinx LVDS

2006-03-07 06:12:00
Hi, I want to findout the minimum accepted voltage difference for LVDS in Xilinx Spartan3 FPGAs. For example is 40mV acceptable? Many thanks for the help in advance.. H aka N ...Xilinx LVDS

Is there any version of Aurora protocol which works with LVDS instead of MGTs?

Massoud - 2007-02-13 20:12:00
Hi All, I reviewed LocalLink and Aurora protocol and it does not specifically say anything about RocketIO tranceivers. So I assumed that it could be implemented by using LVDS pins when higher speeds are not necessary. But its IP just works with RocketIO. - I am wondering if it's possibl...Is there any version of Aurora protocol which works with LVDS instead of MGTs?

LVDS through connectors

Georgi Beloev - 2005-01-19 14:18:00
Hi all, I'm designing a system in which a 4-bit + clock LVDS point-to-point bus has to connect two FPGAs. The two FPGAs are on two different boards--one is on a mainboard and the other is on a plug-in board. What kind of board-to-board connector is recommended for high-speed (~400 Mbps) ...LVDS through connectors

LVDS inputs on Cyclone II

nospam - 2006-05-04 17:29:00
Some time ago I did some experimentation (for a very cost sensitive application) with a Spartan 3 part using an LVDS differential input as a voltage comparator for a crude delta sigma ADC. The I/O bank Vcco was 3.3v the common mode on the LVDS inputs was half the 3.3v supply and the differe...LVDS inputs on Cyclone II

Problems with 7:1 LVDS Tx using OSEDES (Xilinx)

rao - 2007-01-05 17:47:00
Hi, I am trying to make 7:1 LVDS Tx for a display solution (XGA and SXGA) and trying to use the approach as specified in xilinx app note XAPP704 (virtex-4 high speed single data rate LVDS transceiver). The reference design that xilinx provided is for 4:1 (4 parallel data goes to 1 cha...Problems with 7:1 LVDS Tx using OSEDES (Xilinx)

Xilinx LVDS termination resistor

Brad Smallridge - 2005-12-28 14:58:00
How do you turn the 100 ohm resistor on for an LVDS input? I am using the HDR2 header on an ML402 dev board. Brad Smallridge aivision.com ...Xilinx LVDS termination resistor

Bidirectional LVDS

Richard Henry - 2007-06-27 11:39:00
I need to extend a memory-mapped bus into another enclosure and thought that a bidirectional LVDS implementation with serial/ deserializer pairs at each end might work. Does anyone have any experience or guidance on such a setup? ...Bidirectional LVDS

Interconnecting 3v3 LVDS transmitter to 2V5 Receiver

saijayram - 2009-11-15 08:37:00
Hi. Is there any harm in connecting 3V3 LVDS transmitter to 2V5 Receiver..? I am using cyclonII fpga for a receiver in which LVDS inputs are connected to 2V5 powered bank. will the FPGA be damaged with such interconnection..? I am using these lines for clock (26MHz) interconnecting two boards ...Interconnecting 3v3 LVDS transmitter to 2V5 Receiver

DSP-PC architectural advice needed.

soos - 2005-04-18 12:46:00
Hello, I have an idea for a design of a data aquisition system and i am willing to verify the possibility to implement it. Basically it's an ADC connected to the TS201 that sends the entire information sampled to a PC through one of it's LVDS connectors. On the PC there is a PCI Card that k...DSP-PC architectural advice needed.
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