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Modelsim
Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.
We found 1096 threads matching "modelsim"
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The most relevant threads are listed first
problem with Modelsim 5.8 Xilinx Edition
kcl - 2005-02-03 08:10:00
Hi
when i launch ModelSim 5.8c XE, the windows with the logo of modelsim( a
rhinoceros) open and after a few seconds it close and nothing else happen
there no process of modelsim running in the process list of winXP
I don't understand because last week It always run correctly.
I tried to rei...
Problem of uninstall modelsim
fl - 2006-08-13 09:03:00
Hi,
I have installed Xilinx webpack and modelsim in my computer. I find it
is rather perhaps because of the memory not large enough. The webpack
still searches for modelsim for simulation even I uninstalled it
(modelsim). I even tried uninstalled webpack and reinstalled it. It
still looks for m...Problem with Xilinx 9.2i and Modelsim 6.0
2008-06-02 11:58:00
Hi, I`m trying to make a temporal simulation ( Post place & route
model ) of a FPGA designed in Xilinx 9.2i in Modelsim 6.0, but the
Modelsim gives me an error of type Error - (vsim 3193), refered from a
library called swifpli_mti.dll wich Modelsim doesn=B4t find.
I can't get other Modelsim, a...Modelsim GTP_DUAL not recognized
Ruzica - 2009-04-24 07:09:00
Hello all,
I am using Modelsim 6.3 and ISE 10.1 and have a gtp_dual in my
design. When I try to simulate it, Modelsim reports the following
error:
(vcom-1141) Identifier "gtp_dual" does not identify a component
declaration.
I have all the libraries with smartmodels installed in Model...EDK does not find Modelsim
Timo Gerber - 2007-12-04 04:45:00
Hi,
I want to launch Modelsim from within Xilinx EDK.
I have the correct versions installed, the ISE recognizes Modelsim
correctly.
EDK says it cannot find Modelsim, although i have set the following
variables in Win XP:
%MODELSIM% points to the correct modelsim.ini
%MODELTECH% points to th...Xilinx ISE 6.1i+SP2 And Modelsim 5.8
Peng Cong - 2003-11-23 20:12:00
Hi all
I have a problem with Modelsim simulation.
When I use Modelsim 5.7f, I creat a project under ISE 6.1i+SP2, set
Simulator value to Modelsim,
it's fine. But yesterday after I upgrade Modelsim to version 5.8, when I
open the project, it said
that "This project was last saved with t...modelsim
fazulu deen - 2007-08-30 05:21:00
Hai all,
Can any one suggest with an example how to run c++ code in modelsim
simulator...I didnt understand the example mentioned in modelsim user
guide..Anyone tried this??
regards,
fazal
...ModelSim Designer
RobJ - 2006-03-31 11:05:00
Anyone using this tool from Mentor? If so, any comments about it would be
much appreciated. And any comments on how ModelSim + ModelSim Designer
compares to Aldec's Active-HDL environment would be even better. I currently
own ModelSim but am looking for a more complete environment (testbench
...view memory contents in modelsim
hariz - 2009-09-22 07:31:00
i am just a new user of modelsim and debussy, can anyone help me transfer
my code to modelsim and debussy from quartus?
i have a code in verilog using quartus..but due to long simulation time i
can't view all the output..so i switched to modelsim..however, i cant view
the memory contents in model...Please help me!!!!! ModelSim question...
Simone Winkler - 2003-08-27 12:31:00
Hello!
I am a newbie trying to perform a simulation with ModelSim...
I did a (very small) project with the Xilinx downloadable webpack - and as i
wanted to simulate it with modelsim, modelsim closed after the following
line:
#vsim -lib work -t 1ps -L xilinxcorelib testbench
the transcrip...signals in modelsim
=?ISO-8859-15?Q?Benjamin_Menk=FCc?= - 2005-04-29 13:20:00
Hi,
how can I add internal signals to the wave output of modelsim?
At the moment I have to add all the debug sinals to the port of my main
entity.
Another question is, if its possible to save the modelsim settings
somehow? (wave repesentation as integer, scale, etc...)
Do I have to c...Xilinx and Modelsim?
Sunn - 2008-03-31 17:04:00
Hi, please forgive me for any ignorance in this question, but I am
really lost.
I have tried to get Xilinx ISE Webpack 9.2i to work with modelsim. But
it just doesn't seem to work.
Now I am not very familiar with these programs, I am using them
because I am doing a school course that uses F...Modelsim PE vs. Aldec Active-HDL (PE)
Pete Fraser - 2010-03-03 08:02:00
I've finally decided to buy a better simulator
(I've been making do with Modelsim XE so far).
Any thoughts as to the relative merits of Modelsim PE and
Active-HDL (PE) for FPGA simulation?
Thanks
Pete
...Tcl used in Modelsim?
Davy - 2006-04-21 22:34:00
Hi all,
I am new to Modelsim and always use GUI to do all the work.
I heard that we can use Tcl to control Modelsim to compile and run a
batch of work, is there any example available?
BTW, I use Verilog.
Any suggestions will be appreciated!
Davy
...ModelSim
Brad Smallridge - 2004-11-16 19:52:00
I launch Modelsim from the Xilinx IDE. I would like it run all the way
through, to a wait; statement in the testbench. How do I do that? In fact,
since my testbed outputs to text files, I would rather not see the ModelSim
workings at all, and would rather just stay in the Xilinx IDE.
Brad...How to save preferences of modelsim
fl - 2006-09-06 17:09:00
Hi,
The default font of the source window in Modelsim III 6.1e is too
large. Although it is changed after I set it in "Tools-Edit
Preferences", it goes back the default value the next time I open
Modelsim. How can I avoid this? Thank you very much.
...How to get lowest price for a ModelSim license?
Weng Tianxiang - 2006-06-12 14:43:00
Hi,
We want to buy a ModelSim license.
1. Buy Xilinx-ModelSim version license from Xilinx website shop for
$1150 with dongle and 1 year expiration limit;
2. Buy ModelSim PE version from one of agents we contact: $3K for
perpatual license.
Both versions will work and make no differences t...Modelsim XE III 6.x - huge fonts
Dave Pollum - 2008-03-20 15:11:00
I'm trying to run the Xilinx version of Modelsim (XE III 6.2g), and it
displays everything in HUGE fonts. On my 21" monitor, each char is at
least 1" tall. This happens whether I run Modelsim by itself, or when
I run it from ISE Webpack 9.2.04i. I've downloaded the latest
versions of both ISE...ModelSim Xilinx edition new bug?
Dan K - 2006-11-28 17:07:00
Xilinx ISE 8.2i service pack 3
ModelSim XE III 6.1e
VHDL system
When I build a block ram using CoreGen in Xilinx ISE it produces the VHDL
file and the Verilog file.
When ModelSim sees the verilog file it grabs it and trys to use it but then
errors out saying this version of ModelSim does n...Modelsim Warning
FPGA - 2008-02-05 12:51:00
I am getting the following warning in Modelsim
# ** Warning: Design size of 10053 statements or 1 leaf instances
exceeds ModelSim PE Student Edition recommended capacity.
# Expect performance to be quite adversely affected.
When I run simulations, I do not see any waveforms and it just freez...Xilinx ISE : How to make Modelsim reload when design changed ?
Mike Harrison - 2004-12-31 07:31:00
I've been experimenting with ISE Webpack, and have managed to create a simple schematic, and got the
output waveforms in modelsim,
however what I can't figure out is how to get modelsim to reload the new data when I change the
schematic -
After I change the schematic and do 'create schematic s...ModelSim versus Active-HDL....redux
2008-02-11 09:29:00
Hello all,
I'm evaluating ModelSim versus Active-HDL to determine which one is
better in today's marketplace (for VHDL). I found some older threads
that seemed to lean towards Active-HDL so I wanted to see if that was
still the case.
I currently use ModelSim Xilinx Edition but my designs o...Xilinx and Altera Modelsim on the same PC?
Sean - 2004-10-22 13:53:00
Hi all,
I've been using Altera parts and tools for quite a while and currently
have Quartus-II 4.1 on my PC along with the Modelsim-Altera 5.8c.
Now I need to do a Virtex-II design so I obviously need to put some
Xilinx software on the PC. I've used Xilinx devices and tools before
(not the...Modelsim Aliases
Brad Smallridge - 2005-01-12 14:08:00
I would like to spilt up information on a memory data bus into its
components. Some text have suggested aliases as a way of doing it. Is it
the best way? Modelsim doesn't seem to show the aliases that I define, or,
more likely, I don't know how to get Modelsim to show aliases. How is that
don...ModelSim PE exit code 211
Markus - 2007-03-19 20:49:00
When I try to run a timing simulation (simprim is used) modelsim pe
student exits with fatal error and exit code 211.
Modelsim XE works fine, but sloooow.
Does anybody has some experience with this problem and an advice maybe?
...Modelsim XE problem with Xilinx ISE 8.1i and 8.2i
Dan K - 2006-08-24 10:59:00
This is an all VHDL design.
Modelsim XE is installed as full VHDL.
Design uses a number of block rams built with Xilinx coregen, which produces
the VDHL and Verilog files along with a bunch of other files.
Here's the problem that started showing up with ISE 8.1i webpack and is
still there w...Re: Never buy Altera!!!!
Matthew Hicks - 2007-09-27 20:55:00
I prefer Active-HDL, it has all of the same features as ModelSim and a much
better GUI. Plus it has better options for driving signals during a quick
simulation run. Although I did find a bug in a recent past version but it
has been fixed in the current version. The version of ModelSim at t...cannot get compedklib tool to work
2005-05-24 09:00:00
Hello,
I have a problem simulating a design made in Xilinx Platform Studio
with EDK 6.3.
The thing is, I cannot get compedklib to work. It cannot detect my
ModelSim simulator, and therefore it will not compile the libraries I
need for my simulation.
I'm using the 6.3 EDK and ModelSim SE ...Will Modelsim XE 6.3c (Win32) run in Linux/WINE?
arko - 2008-06-15 17:33:00
I've seen messages from regular posters saying that they
run Modelsim/XE Starter Edition in Linux. This evidently
works for the node-locked 'disk-id' based licenses.
But if you have a full license, on a USB-dongle or other
physical key, will Modelsim/XE still work under WINE?
...ISE 7.1 & ModelSim - Simulating Internal Signals
Brendan Illingworth - 2006-01-06 19:32:00
Hi All,
I am using Xilinx ISE 7.1 and ModelSim XE III 6.0 to analze flip-flop and
routing behavior in a Virtex II part. Ports that are declared in my VHDL
entity declaration are simulated and shown in the wave window in ModelSim.
My question is this; how does one specify in Xilinx ISE additio...How to save a changed *.wlf file with ModelSim
Weng Tianxiang - 2006-11-30 21:07:00
Hi,
Our hardware engineer got *.vcd file from Xilinx ChipScope, then I
swithced the *.vcd file to *.wlf file in ModelSim using vcd2wlf
command. After getting *.wlf file, I combined a lot of signals, added
color, changed their display format and so on. After that I would like
to save the file fo...Condition Coverage Using ModelSim
arvi - 2005-10-26 12:10:00
When I use a function that returns a boolean in a 'If' condition,
ModelSim reports that "Condition Coverage ignoring this condition". Is
it a limitation in ModelSim?
...Rocketio, modelsim xe
ndt - 2006-02-13 14:14:00
Hi, I'm trying to implement rocketio on xilinx fpga. Is there a way to
simulate it using modelsim XE. I know for the PE, SE version its using
smartmodels or generating libraries.
Also is there any basic programs using rocketio, architect (wizard can't
simulate, core generator can't compile ...How to oerform a functional simulation of a QuartusII design with Modelsim?
Claudio - 2006-09-28 06:22:00
Hi All,
we are having troubles in simulating our design with QuartusII.
We found that the QuartusII simulator is dramatically slow since every
time we must perform the whole compilation procedure before simulating,
even if we'd like to perform a functional (not timing) simulation; so
we are now...ModelSim is ungraceful with my stupidity...
Gabor Szakacs - 2004-10-21 17:47:00
O.K. I did something stupid, but as a newbie to
both Verilog and Modelsim I expected a nice error
message instead of no indication and no response
while I watched all of my virtual memory get gobbled
up. Then Modelsim closed (was killed by Windows).
All because of:
always PLX_LCLK0 ...ModelSim
Brad Smallridge - 2004-10-15 22:06:00
Where are there some really easy point and click tutorials for ModelSIM?
...ModelSim 6.0 v 5.7 Can't read file
Brad Smallridge - 2006-03-10 18:59:00
When I upgrade(?) to ISE 7.1.4 and ModelSim 6.0
I find my testbenches can not read binary files. Is this
a technical problem or a downgrade on ModelSIM XE
free offering. Note this is a binary file read not a textio file
read which, according to the manual, is still available.
Brad Smallridg...xilinx+modelsim total newbie
2005-03-25 14:48:00
Hi, I have downloaded Xilinx ISE 7.1 webpack and Modelsim 6 free
edition.
I need Xilinx for my digital circuits course.
During the course laboratory we were using Xilinx foundation 2.1. After
designing simple circuit I have attached some probes to inputs and
output and then in simulator bound s...Buggy behaviour in Modelsim, when reading from pipe?
Wojciech Zabolotny - 2006-12-03 09:01:00
Hi All,
I had to integrate a VHDL testbench of complex system with the Python
software (which is used to control the real hardware).
Additionally it had to be done in portable way.
Therefore I've decided to use pipes to establish communication between the
Python software and VHDL simulator....Modelsim Error Code 211
BrakePiston - 2004-02-05 07:42:00
Hi everybody,
I am experiencing a weird problem with Modelsim 5.7d
When i run my .do file with a "add wave" command, the program shuts. I
have run it in command mode and I get that the error code is 211.
Unfortunately, I have not found much about it on the modelsim website.
Can anyone he...