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OPB
Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.
We found 495 threads matching "opb"
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The most relevant threads are listed first
EDK: OPB Question
2006-02-14 16:24:00
Hi all,
I have two questions regarding the OPB usage.
1) why is it the microblaze connects to the IOPB port to the OPB bus
when running from internal memory (BRAM) ? the program runs only from
the ILMB isn't it?
2) PLB-OPB bridge , the PPC405 reference guide says that the PLB should
be used fo...
EDK Microblaze project without OPB?
JD Newcomb - 2007-07-25 15:53:00
Hi, all.
Is it known to be possible to create a Microblaze system without the
OPB?
For example, say I have 1 MicroBlaze with 16KB of d&i BRAM, but I
don't necessarily need the off-chip SDRAM or UART (or any OPB slave
peripheral at all), so I don't include the OPB. And say it's part of a
la...OPB To Wishbone Bridge
2007-04-16 04:07:00
Hi all,
I am looking for an OPB to wishbone bridge to let OPB talk to my IP
via wishbone in EDK. I have read some posts on OPB-> wishbone wrapper
(available at opencores.org). Had a look at the wrapper, which raises
a couple of questions in my mind. Where is the OPB bus translation to
wishbone...problem with Xilinx OPB to OPB bridge
2005-08-01 04:33:00
hello all,
I'm building a system with EDK 7.1 on a virtex4 using Xilinx IP and
soft processor Microblaze .i'm using 2 OPB bus in my design the first
one is my mb_opb and there is another one (opb_2) who is link with
mb_opb through an opb to opb bridge.
My problem is there is no communication fr...OPB versus PLB
Frank van Eijkelenburg - 2004-10-28 03:55:00
Could somebody explain me why the OPB bus is used for "slow" peripheral and
the PLB bus for "fast" peripherals? I have a small design with both an OPB
and PLB bus and both are running at 100 MHz. Of course there is a delay when
access devices at the OPB bus from a PowerPC (OPB2PLB bridge). But..."PIPELINE MODEL" constant in EDK 6.1
arkaitz - 2003-12-05 13:12:00
Hi all,
Has someone tried to attach an user logic core to the OPB bus of
MicroBlaze
using EDK 6.1?
In this new version of EDK there is a new constant called PIPELINE
MODEL that you can find in the user core reference design.
Here you are the options that it gives you:
--USER-- change ...EDK 6.1 vs 3.2 and OPB Bus resets
Carlos Villalpando - 2004-02-20 21:03:00
Hey all.
I'm having a problem with transitioning to EDK 6.1 with a custom OPB
peripheral.
I started out with EDK 3.2/ISE 5.2 with a custom OPB peripheral in a
Microblaze system on a V2 with a well populated OPB bus. That system
works fine, but we have new hardware and need to transistion...creating a custom opb bus master
arincm@hotmail.com - 2005-09-09 19:21:00
Hello fpga-faq,
I want to create a user module that will act as a master on an opb bus.
I am using xilinx Platform Studio, version 7.1i. Now before you say
it, I have read the http://www.xilinx.com/ise/embedded/est_rm.pdf guide
on using the create/import wizard for xps. I have read it, and s...Microblaze PLB vs. OPB busses
Eric Smith - 2007-11-08 20:01:00
Now that Microblaze has support for either PLB or OPB, what are the
advantages and disadvantages of PLB? I started looking at the PLB
specification, but I don't yet understand it well enough to have any
feel for how it compares to OPB, or why it might be preferred.
Thanks,
Eric
...Xilinx OPB BFM simulation error with m_ABus signal
lancos - 2006-09-22 12:40:00
Hi,
I'm developing a custom OPB master peripheral for Spartan3. I don't use
IPIF. During simulation with BFM and Modelsim I noticed that OPB_ABus
is not correct in the following
case: my peripheral loose arbitration but still put a valid value on
the m_ABus (for example 10000), the new master p...microblaze with opb, brams?
Jack - 2005-02-18 00:54:00
hi all
I am wondering if it is feasible for OPB to connect microblaze and
BRAMS.
For instance, OPB connects one microblaze and 2 64KB BRAMS (with
different address map). Each BRAM is instruction/data dual port. So
programmer may consider the system has 128 KB memory space.
How do you fin...Multichannel Opb Memory Controller question
Marco T. - 2006-01-27 04:42:00
Hallo,
I would develop a system based on opb multichannel memory sdram controller.
I would connect Microblaze to the controller using xcl and not opb bus.
I would also connect an external microcontroller to sdram: I thought to
create a custom opb master peripheral and connect it to opb bus....16-bit sdram and 32-bit opb bus
Frank - 2003-12-12 05:31:00
Is it possible to use the opb sdram controller with a 32-bits opb bus to a
microblaze one side and a 16-bits sdram to the other side? What if I do a
32-bits access to sdram. Will the controller convert this automatically in
two 16-bits cycles? The datasheet of the opb sdram controller says: "Sinc...OPB monitor error
2006-03-28 03:43:00
Hi all,
I'm currently verifying an OPB master i/f using IBM's OPB monitor. I'm
currently getting an error 1.11.3, which says I didn't increment the
ABus correctly during seqAddr bus access. The particular case I'm
looking at is this: ABus = 32'h00000E69, and BE = 4'b0111, using
sequential add...Overmapped
Stefan - 2005-07-22 10:39:00
Hi all,
I'm using a Spartan 3 test board with a xc3s200 fpga. Before, I used a
larger device (Virtex II ) and had no problems with my design (microblaze
with my own IP, connected to the OPB-bus). But now, I get errors during the
map process due to the small amount of slices... --> it seems th...c code to initialize a peripheral
2007-06-14 06:55:00
Hi everybody
I am trying to familiar to xps software .So i am trying to create a
peripheral using 2kb bram block in which we can read or write. I have
written verilog code for a bram controller atteched to opb bus.Now i
have to write a c code which perform read and write operation in that
bra...Writing to BRAM using OPB
Bhanu Chandra - 2007-04-15 15:47:00
Hi all,
I am trying to make a peripheral attached to the OPB bus. This
peripheral has a BRAM block in it. The idea is to check how to read
and write to the simple BRAM block and later add some logic to the
controller.
The data to be written to an address range is written to the BRAM
block ...chipscope on opb bus
2005-07-26 10:39:00
Hello, i'm using XPS to build a system based on a Microblaze cpu, and i
would like to add a Chipscope OPB IBA to analyse OPB . I connect it
through my mb_opb but i've got this error
NgdBuild:455 - logical net 'ilmb_LMB_BE ' has multiple driver(s):
pin G on block XST_GND with type GND,
pin O ...OPB to SPI clock frequency ratio
Aaron Curtin - 2006-10-26 09:58:00
Hi, I have a Microblaze based project that communicates to a 16Bit DAC
by means of an SPI interface. I'm using the OPB_SPI interface with a
OPB to SPI clock ratio of 16 (the minimum for this property) which
works out to be a clock of 3.125 Mhz for a 50Mhz OPB bus. This seems
extremely slow con...IP to OPB FIFO
motty - 2007-02-13 22:30:00
I have an IP core than needs to eventually transfer data such that
MicroBlaze (and maybe eventually PowerPC) has access to it. The data
will be pushed out of the IP in bytes. It is possible that only 2
bytes are output for a given 'frame' of data. It is important that
these 2 bytes get proces...How to make Customized IP which connected with Microblaze through FSL access the OPB bus?
fpga - 2006-02-21 17:34:00
I build a system which has a MicroBlaze, a LMB connect BRAM for local
instruction/data memory (8KB) and an OPB connected BRAM(64K) which will
be used as a shared memory for the Microblaze my user defined
coprocessor.
I connected my coprocessor with the MicroBlaze through FSL by using the
tool...OPB BRAM not bein detected
Venu - 2007-02-14 07:15:00
I am trying to design a system which has a BLOCK RAM on the OPB Bus ,
interfaced through a OPB_BRAM_IF_CNTLR.
I first add an "opb_bram_if_cntlr_0" , and connected it as a slave on
the OPB Bus . The system block diagram shows that I have made the
slave connection properly,
Next i add a "br...OPB BRAM not detected in EDK
Venu - 2007-02-26 00:32:00
I am trying to design a system which has a BLOCK RAM on the OPB Bus ,
interfaced through a OPB_BRAM_IF_CNTLR.
I first add an "opb_bram_if_cntlr_0" , and connected it as a slave on
the OPB Bus . The system block diagram shows that I have made the
slave connection properly,
Next i add a "...OPB in Verilog
Andres Calderon - 2004-10-26 09:55:00
Somebody can send an example, document or advice to help me in the
verilog implementation of a OPB module (EDK 6.2)
thanks,
-- Andres
...MicroBlaze and OPB block ram interface controller run at different frequency
David - 2007-02-22 10:56:00
Hello, all:
My question is:
Can MicroBlaze and OPB run at one clock frequency and the OPB block
ram interface run at another? If it is possible, how can I relize it?
Can I change the BRAM_clk someway?
Or would you please refer me some useful document about this
configuration?
Thank you ...MicroBlaze and OPB block ram interface controller run at different frequency
David - 2007-02-22 10:56:00
Hello, all:
My question is:
Can MicroBlaze and OPB run at one clock frequency and the OPB block
ram interface run at another? If it is possible, how can I realize it?
Can I change the BRAM_clk someway?
Or would you please refer me some useful documents about this
configuration?
Thank yo...Accessing Bram
2005-05-31 08:17:00
Which C function should I use to perform read or write into block ram (connected to opb bus with opb bus controller)?
Xio_in8 and Xio_out8 ?
Thanks Marco
...Re: User Core OPB Problem (EDK3.2)
John - 2003-07-07 19:32:00
The ssp0 core has a mir interface within. You need to assign the
addresses for
the mir registers. I.E:
BEGIN opb_core_ssp0
PARAMETER INSTANCE = opb_core_ssp0_1
PARAMETER HW_VER = 1.00.b
PARAMETER c_BASEADDR = 0x21000000
PARAMETER c_HIGHADDR = 0x210000ff
PARAMETER c_mir_BASEADDR ...100MHz Microblaze and 50 MHz OPB
Julien - 2004-12-09 03:43:00
Hello all,
i have a hard time to route my Microblaze sucessfully at 100 MHz
(virtex2 xc2v3000 -5). it seems the limiting point is linked to the
OPB, because i have 2 masters (dopb + iopb) and many peripherals.
here is my question :
is it possible to clock Microblaze with a 100 MHz clock wh...Xilinx EDK OPB bus compatibility
Jordi - 2008-07-19 08:59:00
Hi,
I'm new in FPGA design and I have a question about Xilinx EDK. There
are different versions of the OPB bus. Some cores use newest versions
but others use older versions. So how can I use different cores if
they use different versions of the OPB bus?. Can I put one bridge for
every version...OPB write actions
Frank - 2003-10-23 08:25:00
Hi,
I've succesfully build a microblaze system with external interrupt and my
own IP core (using the opb slave template in the EDK). The interrupt is
connected to a dip-switch. In the ISR I'm writing some data to my own IP
core (which is an OPB slave). My OPB slave is reading some other
dip-s...OPB-to-PLB bridge
2007-03-02 07:22:00
Hi,
I need to access a PLB slave from the Microblaze CPU via the OPB-to-
PLB bus.
The PLB slave requires a cache line when written to. Can I generate
this? It
seems to me that since the Microblaze only writes byte, half-word or
word to the
OPB-to-PLB, the bridge will never do a line write o...OPB master implementation
Venu - 2006-12-24 07:16:00
Hi,
I am designing an OPB Peripheral which has to act as a master and a
slave on the OPB Bus . I am not happy with the IPIF master logic
functionality provided by Xilinx . I am trying to design the master
logic support myself , but the VHDL code for the Xilinx implementation
is not provided i...Is anyone has experience to share OPB for 2 PowerPC in MPMC2 core
js - 2007-04-24 10:12:00
It seems there is problem with OPB in MPMC2 core. PPC will dead when 2
PPC share OPB peripherals in MPMC2 core
...Xilinx OPB Arbiter
imp.chris - 2006-04-20 09:34:00
Hello,
I'm currently building a system with one microblaze and two masters opb
component, But in order to set up priority in my C code, how do i know
the master id of a master component.
Thank you
Christophe
...Peripheral connected to multiple OPB buses
savs - 2006-05-27 14:07:00
Hi,
I was wondering if it is possible to design a peripheral (for
Microblaze) in EDK 7.1 which is connected to more than one OPB bus.
If yes, how can this be done ?
Thanx in advance ....
SAVS.
...How to connect an IP to OPB bus??
Sandip - 2007-03-02 01:44:00
Hi,
I am working with Virtex-4. I have generated a VHDL code and need it
to communicate it with Power PC and some other cores such as UART and
I2C which sits on the OPB. I am willing to connect my IP core to this
bus. can anyone help me how to do this??
Thanks and regards,
Sandip
...Problems with a 4-MicroBlaze Multiprocessor Architecture
sergio.tota - 2005-02-23 03:07:00
Dear all
I'm a new member of this board so a big hello to everybody
I'm experiencing some problems with a multiprocessor architectur
based on the MicroBlaze
I'm using ISE 6.3 and EDK 6.3
I made 2 working multiprocessor systems with 2 CPUs
The first use only one OPB bus and both the proces...chipscope opb monitor
Frank van Eijkelenburg - 2006-07-24 06:24:00
I try to use the opb/iba unit of chipscope to monitor the opb bus within a
simple edk design. I took the chipscope lab example as start point. I am able to
see the OPB signals in chipscope, but I can not set a trigger point. For
example, I want to trigger at a certain address 0xFFFFXXXX. If I ...PLB/OPB Bus Access from ISE
akcooper8@gmail.com - 2006-09-30 19:48:00
Is there an easy way to access the PLB or OPB buses from XIlinx ISE
without going through the PowerPC and EDK?
I am using the XUP Virtex II Pro Development Board and want to
read/write from DDR RAM in ISE rather then EDK for speed reasons.
So I need to access the PLB/OPB buses from ISE which are...