RocketIO
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hanifkagdi - 2006-03-02 08:13:00
Hi,
Actually i am using rocketio wizard 7.1.I want to do conversion of 8 bit
parallel data into serial stream using rocketio mgt for 3.125 gbps.
What frequency i have to apply on
refclk,rxusrclk,rxusrclk2,txusrclk,txusrclk2??
I do not want to use crc and 8b10b module of rocketio mgt.
Please sugg...
John Stein - 2007-12-12 09:21:00
Hi.
I am trying to establish a communication between two RocketIO driven
Virtex2P FPGAs. I am currently simulating the design running into the
following problem: When I set the RocketIO Transmitters (Xilinx
GT_CUSTOM) into parallel loopback mode everything is fine (received data
= sent data). W...
I'm considering the V2pro series for several projects.
I've heard from someone with experience that there are problems with the
RocketIO when a lot of other things are happening on the chip. This is
thought to be a problem with the V2pro package. The evaluation boards
only implement the...
nagaraj - 2007-01-23 00:44:00
Hi,
I m looking for differences between rocketio MGT and GTP (both
architectural as well as the way they are used).
please reply if anybody knows anything in this regard.
Thanks,
Nagaraj
...
sg - 2005-02-07 21:58:00
Has anyone had any sucess in using RocketIO from Virtez 2 or Virtex 4
for Serial ATA applications? From the information collected on various
news groups and web sites, my understanding is SATA OOB cannot be done
using RocketIO in Virtex 2s. Did any one try Virtex 4s?
What is the comment from F...
ndt - 2006-02-13 14:14:00
Hi, I'm trying to implement rocketio on xilinx fpga. Is there a way to
simulate it using modelsim XE. I know for the PE, SE version its using
smartmodels or generating libraries.
Also is there any basic programs using rocketio, architect (wizard can't
simulate, core generator can't compile ...
=?iso-8859-1?B?R2FMYUt0SWtVc5k=?= - 2006-03-21 10:30:00
Hi all,
Did some company already implemented G.709 OTU-2 on Virtex-4 using the
RocketIO?
In other words: the maximum bitrate of RocketIO is 10.3125 but OTU-2 is
10.709. Should Virtex-4 be definitively excluded or are there some
tricks to achieve that challenge?
Cheers
Mehdi
...
vt2001cpe - 2006-08-24 15:22:00
Anyone have experience with directly driving a cable with RocketIO? I
am interested in any information/experiences/advice regarding linking
two FPGAs via RocketIO over a cable. I have seen some signal
characterization information for high-speed links over copper, but
usually less than 800Mhz. I ...
johnp - 2006-06-22 16:47:00
I'm connecting a V2Pro Rocket IO to a Agilent optical interface and
am having problems getting the RocketIO receiver to reset properly
and generate the correct data. The design originally used a Vitesse
serial parallel interface chip and that worked fine. Since we have
a spare RocketIO, we'd ...
Just as the subject says I am looking for someone local who has experience
in using RocketIO and possibly Aurora protocol for simple data streaming.
This is a contract position.
Thanks,
/Mikhail
...
Peter Mendham - 2006-08-02 09:24:00
Dear all,
I'm in the early stages of designing a board with a Virtex-4 FX on it
which we are planning to use for development involving RocketIO. The
other guys on the team have stated that it would be "really useful" to
have the clock for the RocketIO fed from a programmable oscillator. W...
Massoud - 2007-02-13 20:12:00
Hi All,
I reviewed LocalLink and Aurora protocol and it does not specifically say
anything about RocketIO tranceivers. So I assumed that it could be
implemented by using LVDS pins when higher speeds are not necessary. But its
IP just works with RocketIO.
- I am wondering if it's possibl...
Hi,
I am presently working on a design involving a RocketIO in a Virtex II
Pro. I am looking at reference clocks for the PLL of the RocketIO
meeting among other things the jitter requirement related to the serial
link frequency. I am wondering how to combine deterministic jitter and
rando...
Peter Mendham - 2006-08-08 08:24:00
Dear all,
I'm new to RocketIO and would appreciate any guidance from a hw design
perspective. I am currently doing schematics for an application
specific development board and trying to work through the various
demands from the datasheets and app notes, for example, the fact that it
seem...
Hi all,
I am thinking of using RocketIO for serializing a very simple parallel data
flow from one Xilinx FPGA to another. The data flow is a stream of 16-bit
word pairs running at approximately 70 MHz, i.e. the total data rate is 2.24
Gb/s. At the receiving end I need to resynchronize the data...
2005-03-10 14:20:00
Hello ALL,
I am designing device, based on Virtex-4 FX20 chip. This device is
going to produce lots of data and I would like to send it to processing
computer using Gigabit Ethernet interface. I am lucky to have two
Ethernet MAC's built-in in the FPGA. Also we would like to use
RocketIO trans...
tullio - 2008-02-13 09:24:00
I am using for the first time a Xilinx RocketIO module (I have years
of FPGA experience though); normally I prefer to explicitly write on
my code all the instatiations.
Manual UG196 says:" The RocketIO GTP Transceiver Wizard is the
preferred tool to generate a wrapper to instantiate a GTP_DUAL
...
John - 2005-04-26 23:28:00
Anybody can advise me to configure the RocketIO attribute correctly to
emulate TLK3101 or TLK2501 SerDes.
John.
...
John - 2005-04-26 23:28:00
Anybody can advise me to configure the RocketIO attribute correctly to
emulate TLK3101 or TLK2501 SerDes.
John.
...
Dale - 2007-01-11 13:44:00
Is it just me or is the documentation for the RocketIO (MGT) for the
Xilinx Virtex4 very bad? I'm trying to find duty cycle requirements
for the MGT clock. Is it OK to use a clock with a 40% duty cycle?
Also, if anyone can point me to some better RocketIO (MGT)
documentation for the hardware...
Hi,
We have a VirtexPro40 on a PCI-Express board. Right now we want to
write some
rtl to test the RocketIO inside of the FPGA. Since I am new to this
area, can anyone suggest some plan for testing. we have eight LED
connected to the FPGA.
Thanks.
Jin
...
jfh - 2005-08-03 03:11:00
Hi,
I work on a project involving an optical link. The transceiver is a
finisar one with a CML interface and AC coupled serial links with
internal 100 ohm differential impedance termination for the receiver of
the optical transceiver. I use one RocketIO in an XC2VP7FF672-6I with a
BREFCLK run...
colin - 2006-06-30 06:49:00
Does anyone have a feel for at what point rocketIO simulation becomes
necessary.
I have an FPGA right next to my PCIExpress card fingers so I have not
simulated (I don't have the tools). But I now ideally need to move the
FPGA about three inches away and I'm starting to wonder.
The board is...
2006-10-12 03:10:00
May I use rocketIO (Virtex2PRO) in custom mode for
serialize/deserialize STM-1 (155.52 Mb) ?
...
Paul Johnson - 2006-02-05 17:48:00
Xilinx has a report on Infiniband cable characterisation with RocketIO
MGTs (v2.0, May 10th 2004,
http://direct.xilinx.com/bvdocs/reports/ug043.pdf). Unfortunately,
this is vague on BER measurements. The intro states that BERs are
presented for various configurations but, in the event, the data
...
Josh Rosen - 2006-08-06 21:19:00
Has anyone been able to dynamically change the SerDes speed on the V4FX
RocketIO. I've been able to get the RocketIO to operate correctly at both
SDR rates (2.5GHz) and DDR (5GHz) rates using static parameters but when I
try to change the speed dynamically the RocketIO enter a state where they
n...
John - 2005-04-26 23:28:00
Anybody can advise me to configure the RocketIO attribute correctly to
emulate TLK3101 or TLK2501 SerDes.
John.
...
Josh Rosen - 2006-08-08 10:05:00
Has anyone been able to dynamically switch speeds on the V4FX RocketIO?.
I've been trying to switch between 2.5GHz and 5GHz using the
reconfiguration ports. It works in simulation but not in real hardware.
Has anyone else tried to do this?
...
Dear Xilinx (and others with RocketIO/X, PCIe experience),
I am very interested to know how the Xilinx PCIe Solution works.
As far as I have been able to determine there are several problems:
1) Rocket IO does not have direct control of TX enable,
PCIe TxElecIdle is specified as Vdiff 50 ...
I am currently using version 1.7 of the VHDL Aurora 401 reference
design for Xilinx Vertex II Pro RocketIO interface and trying to find
a way to bypass 8B/10B. What I do is to change the configurations of
ports and attributes of GT_CUSTOM as suggested in RocketIO transceiver
User Guide (page 59 ...
Denkedran Joe - 2008-06-06 11:31:00
Hi there,
I'm designing a PCB that incorporates a Virtex4 FX60 with 16 RocketIOs. All
RocketIOs function only as a receiver and I wonder if you should care for
length compensation on my FR4 board, anyway. The reason I am not sure is
that in my opinion each RocketIO synrchonizes itself indep...
=?ISO-8859-15?Q?Benjamin_Menk=FCc?= - 2005-04-10 16:21:00
Hi,
I want to connect a LCD Panel with LVDS to my Virtex2Pro. The LVDS
frequency is max 80 MHz. My fpga runs at 100 MHz and is speed grade -5.
Do I have to get into the RocketIO stuff now, or does it have nothing to
do with it?
regards,
Benjamin
...
I'm looking at using a V2P RocketIO transmitter to synthesize a clock by
bypassing the 8B10B encoder and feeding it 01010101 data words. I would
vary the output clock frequency by varying the reference clock and/or
the data pattern (00110011, 00001111, etc.). Is there any reason this
would not w...
Antti - 2006-03-17 08:46:00
xilinx rocketio is not fully SATA compliant so the SATA sockets on
ML300 and XUPV2P are just someones
"wishfull thinking.." !
on the ML300 I did someting useful with the SATA connector, namly I did
take a SATA cable cut it half, soldered a buzzer onto it, then plugged
into SATA connector on...
2005-02-10 21:46:00
Hi,
We are using RocketIO (1GHz Fibre Channel) in 32-bit mode in a
Virtex-II Pro 50. We are using the CUSTOM_GT and believe that all the
attributes are set correctly. The problem we are having is in our
simulations. When data is received it seams that the Comma character
is mis-aligned. A...
2007-06-21 15:18:00
Hello folks,
I am using the V5 rocketio to implement a high speed serial IO. I have
configured the GTP and it works , but the only problem is that the
first 5 words ( comma and data) are corrupted at the receiver. I also
ran the example design and it also reflects the same problem. Hence I
g...
Xilinx has lost my account somehow so that I am unable to log on their web
support page... so I thought I'd try it here...
Which of the two should I use if I want to generate simple separate
streaming tx only and rx only cores for V4FX? The RocketIO wizard allows for
choosing silicon step leve...
sovan - 2006-08-03 20:21:00
I am trying to simulate RocketIO MGT in VCS. When I do
vcs -lmc-swift-template GT_SWIFT
it says it couldn't find libswift.so library. I am using Red Hat
Enterprise Linux WS release 3. What files/directories should I look for
to confirm if the SmartModel Library is installed in VCS? or any bette...
Hi everyone,
Could someone with experience or simulation tools provide information on the
hardware requirements to interconnect Virtex2pro and Virtex4 with rocketio
at 2.5Gb/s.
The simpler the better, DC if possible and if not AC. I'd like to know the
termination voltages and anything need...
I know this may seem like a strange question but what is the minimum
bitrate that data can be sent through the RocketIO port?
Just another question while I'm here, anyone Xilinx people out there
really familiar with the Xilinx ML310 board with the Virtex-II pro fpga?
I just want to know wha...
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