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SDRAM
Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.
We found 733 threads matching "sdram"
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The most relevant threads are listed first
SDRAM controller.
2005-11-10 21:56:00
Hi Guys,
I am writing a SDRAM controller (for the first time), its a Micron
MT48LC16M16 sdram. I am having a little trouble coding it, i've written
some code for it but i am not sure if i am going along the right path
or not ? Does neone has a little tutorial on how to code a sdram
controller...
For accessing my SDRAM,what should i do?
ARRON - 2005-05-18 09:22:00
I try to access the SDRAM in my program, and wait for enough time before writing data to SDRAM,but i find the value of SDRAM is FF,what should i do ? what is wrong?
...SDRAM problem
cool.rezaul - 2009-07-02 23:08:00
Hi I am using Kingston 512MB SDRAM for my XUP virtex 2 pro development
board. I am working on image filtering where I have to transfer the image
file to the SDRAM and then filter it by bring the data to the BRAM's. I am
struck off into following steps:
1. How can I send a whole image file to the ...can someone recommend a board?
Subhasri krishnan - 2006-10-25 15:37:00
Hi all,
After some hardware problems with our protoype I have been advised to
use a board. But I cannot find one with all the features.
1) VGA in and out ports
2) SDR SDRAM.
I have looked at digilentinc and xess but these people dont have any
that fits all requirements. I have the XUP V2P boar...SRAM to be able to Read/Write SDRAM
Vick - 2004-11-06 02:48:00
Hello All,
I have questions regarding a project i am currently working on.
I have been assigned to develop an SRAM interface to be able to
Read/Write an SDRAM (Micron 168-pin).And the SRAM should maintain its
own functonality i.e. the SRAM itself can be read/written. Also,
whatever data is r...ALTERA EPXA1 SDRAM BUG
Ralf - 2005-05-20 06:57:00
Hi all,
have everyone experience about a second SDRAM with the Altera
FPGA+HARCORE-CPU EPXA1?
Its is unpossible for me to access the second SDRAM.
I used a modified "Hello World" program from ALTERA, Linux running on the
hardcore CPU and ARMBOOT to address the second SDRAM (Chip-Select SD-CS1...store program in external sdram
Tom - 2003-11-24 03:39:00
Hi,
How do you store an entire program in external sdram, is it possible
to declare all sections in the linker script to sdram (eventually the
boot section to bram) ? Or is there another way to get all data in the
sdram ?
thanks
Tom
...xilinx VP20 and SDRAM
qudhs - 2004-10-12 10:38:00
Hi!
I have a XilinxVP20 chip with 2 PPC cores and a 32M SDRAM. what I want
to do is to use the SDRAM as instruction memory for one of the PPC
cores, but I couldn't figure out how to upload the instruction data onto
the SDRAM.
thanks in advance!
-yang
...how can i save my received data into the SDRAM?
ARRON - 2005-05-13 04:51:00
I have receive large character data from RS232, i want to save it in the SDRAM memory, i find the SDRAM is 8M*32, but the character is 8bits,not 32bits, if i write a character into an Unit of SDRAM, next 24bits memory is wasted, and i find some data is not correct, how can i use the SDRAM correctly ...SDRAM controller
FP - 2008-06-09 10:22:00
I am looking for a SDRAM controller for Xilinx Spartan3 device in
Verilog. xapp 134 has one which targets virtex 2 devices. Xilinx MIG
can be used for DDR and DDR2 SDRAMs. Can a DDR SDRAM controller be
used to drive SDR SDRAM?
What other options do I have?
...Altera SDRam ip core
Nick - 2005-05-05 06:03:00
Hello,
I interface my Cyclone with a micron SDRam using the Altera SDR SDRAM
Controller but it seems that there is something very wrong in what I
do.
When I send a write command to the controller, what I get on the
output using SignalTap is the write command issued to the SDRAM, but
only 2...SDRAM in SPARTAN 3E
Pablo - 2006-12-14 04:44:00
Help!!!!!!!!! Hi, How can I write data into the ddr sdram with
Microblaze and the OPB DDR. The SDRAM is 16MX16 and I have only found
how can I test this memory. Can anyone tell me something about this????
...why my SDRAM test failed in EDK7.1i?
ARRON - 2005-06-08 03:09:00
I have built a new project with two SDRAM(each 32M) in EDK7.1i,and used the original memory test program,i find the first SDRAM test is successful,BUT the second SDRAM test has failed,Why?What is wrong with it?
Any advice is appreciated!!!
...SDRAM Controller
George - 2003-10-26 07:19:00
Hi!
I am a bit new to FPGAs, so far I have only worked with CPLDs ( Xilinx
9500 family ). Now I would like to use a Spartan 2E ( with WebPack 5.2
and VHDL ) to make a SDRAM controller.
I have searched this archive but I haven't found any topic related to
my question. Here's the deal. When dat...DDR2 SDRAM and Virtex2Pro
Sean Durkin - 2004-09-07 03:43:00
Hi *,
does anyone have any experience with DDR2 SDRAM-controllers in a
Virtex2Pro? There's of course a bunch of ready-to-use controllers for
DDR1 SDRAM, but for DDR2 it only says in Xilinx' "Memory Corner" that
"The Virtex-II Pro built-in capabilities enable DDR2 SDRAM interfacing
at data ...SDRAM Reading problem
raju_lingala - 2006-02-20 15:02:00
Hi all, I am new to this group and i am facing one problem regarding
reading from the sdram.
Actually I am accessing sdram indirectly through CPU. So I am writing
write data into the fpga registers and set the wr_start bit, after
completing the write operation wr_start bit will be cleared indicatin...SDRAM controller
RANGA REDDY - 2004-05-26 07:02:00
Hi all,
can anybody tell how autorefresh in SDRAM exactly works? suppose in
SDRAM specifications it is mentioned that 64 ms, 4096 cycle
refresh(15.6 us/row) what exactly it means and how we need to generate
the autorefresh cycles.
actually i am trying to upgrade the 512k*4*32 SDRAM(Fujitsu ...DDR SDRAM controller for virtex 2 pro
ralstef - 2007-02-01 23:53:00
I want to use a DDR SDRAM on my virtex 2 pro platform; however the
vhdl controller available is for a 256Mb micron SDRAM; mine is a
kingston kvr266x64c25/512 with 512MBytes ( actually 64Mx64).
Can anyone help me? is it possible to adapt the opencore controller
for my SDRAM? how??
...debug application in sdram (microblaze system)
Frank van Eijkelenburg - 2004-02-11 11:27:00
Hi,
Is it possible to debug an application which is in sdram by use of xmdstub?
I have a small bootloader program which programs a final application into
sdram (by use of xmodem). Now I want to debug this application, is that
possible or should I use the opb mdm device?! If it's possible, I gu...read & write on SDRAM speed with PPC 300 MHz
Pierre - 2005-06-29 07:07:00
Hello
I use a Virtex-II Pro with PowerPC at 300 MHz, 8 kB IOCM, 32 kB DOCM and
external 32 MB SDRAM (connected on PLB )
When I read 10 times 32 MB on my SDRAM, that takes 3.7'' and when I write
the 320MB on the SDRAM it takes 9.6'' without burst support and 6" with
burst support.
Did s...SDRAM Controller timing problem
etrac - 2004-01-07 04:33:00
Hello,
I have implemented my own SDRAM controller in a Virtex II component in
order to use SDRAM modules Sodimm-PC133 (133 MHz frequency).
My problem is that this block seems to work very well with MICRON
Sdram modules, but it is not fully stable with SMART modules. It seems
to be the burst...DDR SDRAM demo for Spartan-3E starter kit?
2008-01-05 06:31:00
I have a Xilinx/Digilent Spartan-3E starter kit Rev D (with 46V32M16
-6T F).
Is there any *simple* demo that stores a picture bitmap in the builtin
DDR SDRAM and sends the bitmap to the VGA port continously ..?
Is it correct that the DDR SDRAM won't go below 75 MHz due the DLL
used ..?
(Micr...SDRAM
RANGA REDDY - 2004-05-26 02:27:00
Hi all,
can anybody tell how autorefresh in SDRAM exactly works? suppose in
SDRAM specifications it is mentioned that 64 ms, 4096 cycle
refresh(15.6 us/row) what exactly it means and how we need to generate
the autorefresh cycles.
actually i am trying to upgrade the 512k*4*32 SDRAM(Fujitsu ...large data access to SDRAM at fixed frequency
mpierrotb - 2006-07-28 17:52:00
Hi !
I am new in electronique.
I want to make an analog acquisition board with an ARM microcontroler (
Samsung S3C44B0x 66MHz) with
a 8Mbytes SDRAM and an A/D converter( Analog AD775 ).
The sampling rate of the A/D converter is at 30Mhz, and i would like to
connect its digital output to the S3...NIOS II - Instantiating array on SDRAM
zg - 2004-08-13 17:03:00
Hi group,
I am trying to develop a digital camera around the NIOS II using the
Stratix development board.
I need to instantiate a large buffer (2MW) in the SDRAM.
In my code I instantiated my array like this:
alt_u16 Image_Buffer[0x2000000] __attribute__ ((section (".sdram"));
The SOPC b...16-bit sdram and 32-bit opb bus
Frank - 2003-12-12 05:31:00
Is it possible to use the opb sdram controller with a 32-bits opb bus to a
microblaze one side and a 16-bits sdram to the other side? What if I do a
32-bits access to sdram. Will the controller convert this automatically in
two 16-bits cycles? The datasheet of the opb sdram controller says: "Sinc...how to speed up the program running in ddr sdram
Athena - 2006-01-09 10:02:00
Hi all,
At present, I am using Xilinx SPARTAN XC3S1500 FPGA with Micro MT46V16M16 to do some projects. As my programme is very large, there is not enough space to put them in the bram, so I have to put them in the ddr sdram. However, I found that when the programme is in the ddr sdram, the speed ...Sdram controller on the Altera Cyclone board!
kingkang - 2005-04-07 04:17:00
Hi
I wrote a sdram controller which has pass the RTL simulation.
But when it come to the Altera cyclone board,the read/write
data were wrong.I have written sdram with some data,and then
I read the data from sdram.But found the data is not equal to
what have been written into the sdram.One or So...VHDL CODE FOR SDRAM IN SPARTAN 3E
Pablo - 2006-12-18 06:28:00
Does anyone try to read values from sdram without the use of
Microblaze?. It is simple to read/write values in ddr sdram with the
use of pointer in MIcroblaze but how can you read values in vhdl code
for displaying an image (store in sdram) with the use of a vga core.
...SDRAM Controller on a cyclone dev kit
Nick - 2004-08-15 07:58:00
Hello,
I've been unsuccessfully trying to use the SDRAM on my MJL Cyclone dev
kit. I've tried the example (not very well documented) sold with the
dev kit, and tried the Altera IP Sdram controller.
The way i do it :
I connect the sdram controller to the sdram and use a small test
module to...Spartan3 interface with DDR SDRAM
FP - 2008-06-05 10:24:00
I would like some suggestions on interfacing the Xilinx Spartan3
device with a DDR SDRAM. The idea is to build a controller that will
set up the DDR-SDRAM so that I can do a burst read of a page of data
into a block of internal SRAM (dual port).
Your help is appreciated
...How much time margin should I give to a SDRAM interface via FPGA?
news reader - 2007-04-01 05:00:00
My altera FPGA is connected to a SDRAM on the prototype board.
Assume the clock frequency is 100MHz, how much margin should I
give to the SDRAM? 3ns? 5ns?
...Increase Memory Resource in SDRAM.
Pablo - 2007-04-25 07:59:00
Hi, I have a project with a big requeriment of memory. So I have
decided to generate a linker script with every section to SDRAM. The
problem is that I don't know how can I increase the "default memory
area" for my app. The reason is that I do "xil_calloc", but when I put
a big number I receive ...MPMC2: MPMC2 with DDR2 SDRAM
zyan - 2006-11-13 04:15:00
Hi,
Has anyone successfully used MPMC2 as the memory controller for DDR2 SDRAM? I used it to interface with the Micron's MT47H32M16CC-37EB DDR2 SDRAM and it doesn't work. Any important steps/settings required in order to get it working?
Thanks.
...Sharing SDRAM on Stratix II DSP Development kit
2005-08-21 12:39:00
I would like to implement a design that shares the external SDRAM that
is installed on the Stratix II DSP Development Kit board between the
Nios II controller and custom circuitry that will occupy a portion of
the remaining Stratix II LE's (ALM's).
Half of the SDRAM would be dedicated for coll...external sdram and gdb tool
Tom - 2003-11-26 05:14:00
Hi,
I have some project where I store my entire program in the external
sdram (by redirecting every section in the linker script to the
sdram). When I download the program to the board, it doesn't work.
When I run the program in the debugger tool, it works. Does anybody
know an answer to thi...Xilinx user constraints with respect to output clock from the design
gangireddy.p - 2009-04-07 10:47:00
Hi,
Sdram signals are going out of my design to a SDR SDRAM. This SDR SDRAM
requires a setup time of 3.8 ns. The clock to SDRAM is provided by the
design which is generated from the DCM with the source clock at 40 Mhz. I
tried to put output constraints on other SDRAM control signals with respect
...xilinx spartan3e kit ddr sdram
emu - 2007-06-12 13:10:00
Hi all,
is there any open source DDR SDRAM controller IP available (VHDL) for
the DDR SDRAM on this kit ?
...read & write on SDRAM speed with PPC 300 MHz
Pierre - 2005-06-29 07:10:00
Hello
I use a Virtex-II Pro with PowerPC at 300 MHz, 8 kB IOCM, 32 kB DOCM and
external 32 MB SDRAM (connected on PLB )
When I read 10 times 32 MB on my SDRAM, that takes 3.7'' and when I write
the 320MB on the SDRAM it takes 9.6'' without burst support and 6" with
burst support.
Did s...SRAM to be able to read/write Micron SDRAM
Vick - 2004-11-08 00:31:00
Hello all,
I had psted this question earlier but havent got any response yet...
I was wondering if the questions I asked made any sense (or) were they
just out of the way... So again, I have the Micron SDRAM Verilog code
and I need to make SRAM read/write the SDRAM... Obviosuly, the SRAM
sho...