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SRAM

Comp.Arch.FPGA is a worldwide Usenet news group that is used to discuss various aspects of Field Programmable Gate Array (FPGA) based computing systems development.

We found 656 threads matching "sram"

You are looking at page 1 of 17.

The most relevant threads are listed first

SRAM to be able to Read/Write SDRAM

Vick - 2004-11-06 02:48:00
Hello All, I have questions regarding a project i am currently working on. I have been assigned to develop an SRAM interface to be able to Read/Write an SDRAM (Micron 168-pin).And the SRAM should maintain its own functonality i.e. the SRAM itself can be read/written. Also, whatever data is r...SRAM to be able to Read/Write SDRAM

Control asynchronous SRAM like synchronous SRAM

Michael Dreschmann - 2005-05-28 09:43:00
Hello, I've an Virtex II (later it'll be a Spartan 3) witch is connected to external asynchronous SRAM. Now I would like to access it in the same way as a synchronous SRAM (like a BRAM for example). I think reading should work in the same way as with an synchronous SRAM (set address and /oe a...Control asynchronous SRAM like synchronous SRAM

Can use SRAM instead of VRAM ......... how ???????????

fahadislam2002 - 2005-08-08 20:17:00
Hi.. i wanna use sram instead of Vram in my project ... according t my knowledge vram is same as sram but its dual port...........as fo display its needed to read and write at same time fastly ...so use dual port sram...... bu problem is ... i m available only sram whic...Can use SRAM instead of VRAM ......... how ???????????

Displays an image in the XS Board RAM on a VGA monitor

greenplanet - 2005-03-03 23:02:00
Dear all, This may sound stupid to ask, but I am very frustrating now as my deadline is approaching. I want to make use of the VGA generator example on www.xess.com. How could I write/read data to the specific address of the SRAM? I would have to have a SRAM controller that writes and reads...Displays an image in the XS Board RAM on a VGA monitor

Re: Xilinx - Proper VHDL for Bidirectional Pins

Inquiring Guy - 2004-08-23 20:29:00
You should use tri-state buffers. SRAMDQA 'Z'); x What is the proper VHDL code for bidirectional pins on a Xilinx chip? > I used the code below but the chip runs hot. > > > SRAM BIDIRECTIONAL PINS:process(SRAM W SIGNAL 5,SRAM DQA SIGNAL 5,SRAM DQ > B SIGNAL 5 ) > begin > ...Re: Xilinx - Proper VHDL for Bidirectional Pins

SRAM bidirectional bus

ALuPin - 2004-02-24 09:48:00
Hi, I have a question concerning the VHDL description of a bidirectional bus. This bus comes from (goes to) an SRAM which I try to simulate with a corresponding VHDL model. Now I have an INOUT pin at my SRAM-Controller : Sram_data : inout(7 downto 0); Within my SRAM-Controller I have ...SRAM bidirectional bus

Simulation MODEL for SRAM

ALuPin - 2004-02-19 04:21:00
Dear Sir or Madam, I want to design an SRAM controller for the asynchronous SRAM IDT71V256SA. Can somebody tell me if there is such a VHDL simulation model available? Thank you very much. Kind regards A.Vazquez G&D SystemDevelopment ...Simulation MODEL for SRAM

how i can use the external SRAM of FPGA

2009-05-12 11:13:00
i tried a description of RAM but i can't syntesize it and i have the following error: ERROR:Pack:18 - The design is too large for the given device and package. i think i will be to use the external SRAM FPGA's board, but i don't know if i can use it without EDK and how i can read and write ...how i can use the external SRAM of FPGA

NIOS SRAM Problem with Stratix

2005-03-08 18:48:00
We have a NIOS design running at a clock speed of 92 MHz in a Stratix part that will have Flash and SRAM. All of our program memory is to reside in SRAM(IDT714V416L) after boot from flash. We are able to run the debugger on one out of 10 of our boards but the other 9 seem to be having problems...NIOS SRAM Problem with Stratix

Nios memory

cruzin - 2004-01-13 19:36:00
I have an SRAM controller Avalon slave we created which Nios can successfully access to read and write SRAM. My question is: I can not set the program or data memory address in the Nios setup screen to this memory. Why not? Also: How does Nios determine where a malloc() will allocate memory ...Nios memory

Hve to know the pin connection between cpld and fpga in my design

senthil - 2004-10-12 09:48:00
Hi Friends, In my board i have SRAM, Spartan-3 FPGA ,CPLD Xc95144xl and PC104 Connector (ISA bus header). I want to pass the data stored in SRAM to PC104 . in between that with the help of spartan-3 only data stored in SRAM. ____ ______ ______ _______ |pc | ...Hve to know the pin connection between cpld and fpga in my design

Digilent SRAM Controller

al99999 - 2005-12-15 07:50:00
Hi, I was wondering if anybody had designed a vhdl sram controller for the Digilent Memory Expansion board that is designed for the spartan 3 starter kit. It is just two ISSI IS61LV5128AL sram chips. I have tried writing a controller but cant seem to get it to work!! Thank a lot, Al...Digilent SRAM Controller

Quality of timing simulation

ALuPin - 2004-05-18 05:13:00
Hello newsgroup users, I have made a timing simulation for my SRAM-Controller and an external asynchronous SRAM. I have used the FPGA Cyclone timing output file for my SRAM-Controller and the extra timing file for the SRAM model. Both components have been instantiated in a testbench. H...Quality of timing simulation

Warning appeared while inferring SRAM on xilinx Virtex-E by synplify 7.3.1

boku0712@gmail.com - 2005-04-27 01:09:00
Dear all, While I tried to infer SRAM in synplify7.3. It came out the following warning. Though I see the log and 7.1 did gen the SRAM by Block RAM. I wonder if there's any answer or solution to this warning. Thank you very much!~ @W: Could not implement Block RAM. Is the read address reg...Warning appeared while inferring SRAM on xilinx Virtex-E by synplify 7.3.1

Re: RAM Synthesized away

Brad Smallridge - 2005-04-01 14:05:00
Don't know this software but perhpas there is a switch to keep it from optimizing the SRAM away. Can you bring the SRAM outputs to IOs? ...Re: RAM Synthesized away

ML505 - How to read/write SRAM?

charlie78 - 2009-01-21 10:53:00
Hi all, I'm an Italian student, I'm new in fpga and Microblaze implementation. I saw many starting tutorials about ML505 Xilinx Platform and usa of Xilinx Platform Studio 10.1 and EDK. In these tutorials I did not found any example of reading and writing operation of the SRAM. My code reside in ...ML505 - How to read/write SRAM?

how to use ram or memory

The Lord of War - 2009-07-02 23:08:00
hi all i'm new to the fpga field i was wondering how do i use the onboard sram, i need to create a big memory structure so do i just do: type dataout is array (0 to 1048576) of std_logic_vector(15 downto 0); signal mem_struct : dataout; and the fpga knows what to do and where to save the ...how to use ram or memory

configuration SRAM cells in Xilinx/Altera FPGAs

raj - 2004-07-27 02:24:00
Hello everybody, I am not new to the world of FPGAs but have not found enough literature regarding the SRAMs used for configuration. I need some inputs, help or pointers(papers, articles) from the FPGA community regarding these. There are very few literature relating to this(May be I am no...configuration SRAM cells in Xilinx/Altera FPGAs

Interfacing FPGA to on-board SRAM Stratix EP1S40F780C5

Edward - 2004-06-11 06:29:00
Hello All, I am trying to interface the on-board SRAM (IDT71V416 256Kx16) to the FPGA on the Stratix. It is not installed among the library components in the SOPC builder so I cannot instantiate it automatically. I have the datasheet for the SRAM but I need to know where the address, data p...Interfacing FPGA to on-board SRAM Stratix EP1S40F780C5

Problem with writing values to SRAM from XMD

Roman - 2007-04-25 11:37:00
Hello! I am using a board with Virtex4 PPC405, external asynchronous SRAM memory and EDK 8.2i. If application program resides in BRAM and I want to write and read from SRAM, it is only possible if there is instruction and data cache enebled and I add XCache_EnableCache in the beginning of the...Problem with writing values to SRAM from XMD

Accessing SRAM on the Spartan-3 Starter Board

jmariano - 2007-05-10 08:25:00
Dear All, I'm sure this question was already been posted (and answered) in this list, but I could not find a suitable answer for my little knowledge of this matters, so, with my apologies, i'm posting it again. I'm developing a microblaze system based on the Spartan-3 starter kit board. I...Accessing SRAM on the Spartan-3 Starter Board

SRAM to be able to read/write Micron SDRAM

Vick - 2004-11-08 00:31:00
Hello all, I had psted this question earlier but havent got any response yet... I was wondering if the questions I asked made any sense (or) were they just out of the way... So again, I have the Micron SDRAM Verilog code and I need to make SRAM read/write the SDRAM... Obviosuly, the SRAM sho...SRAM to be able to read/write Micron SDRAM

Approximate power and area values for a 1-bit SRAM cell.

2006-02-18 16:02:00
Hi, Can some one give an insight about the *approximate* values of power and area consumption of a 1-bit SRAM cell for 0.13 micron technology. We need to approximate the area of 4-input LUT and our synthesis tool does not support SRAM standard cells in its library. It synthesises a DFF as mem...Approximate power and area values for a 1-bit SRAM cell.

ISSI SRAM.

ertw - 2008-03-15 10:11:00
Hi, I have a simple question about memory organization. I would like to write a memory controller for IS61LV25616AL SRAM (256K x 16) but I am having trouble understanding how the memory organization works. Datasheet says the memory is organized as 262,144 words by 16 bits which is 256K x 16...ISSI SRAM.

Onchip SRAM Vs Registers

2005-03-25 10:39:00
Hi all, Can anyone tell me what is the threshold point(memory size) to opt for Onchip SRAM instead of FlipFlops , considering the Power&Area. In a module I have ~5Kbit of memory implemented as verilog registers. I would like to know the Power/Area savings if I switch to SRAM instead of Flipf...Onchip SRAM Vs Registers

SRAM on spartan3 board

fpgawizz - 2005-03-05 10:43:00
Folks I am trying to write and read from an address location of the ISSI SRAM on the spartan 3 board. Basuically i tried to write a state machine that represented the timing diagram of the read and write cycle of the SRAM. Does anyone know of a simple way to try writing an 8-bit data to a locat...SRAM on spartan3 board

MicroBlaze & SRAM

Ben G - 2004-09-27 10:47:00
I have an EDK design with a MicroBlaze processor and use the External Memory Controller (EMC) to get access to off-chip SRAM. I access the SRAM from c using a pointer and have a loop in my program that writes a value and increments the pointer to the next address. As I am using a pointer t...MicroBlaze & SRAM

Boot : Sram Problem

Johann Waldherr - 2004-09-28 12:40:00
I am working on a Xilinx V2P4 FPGA design with an PLB EMC. I can execute programs from 16bit wide SRAM when they are downloaded with Xilinx's XMD. Now i wrote a bram bootstrap loader that copies a fw image from flash into sram and then jumps to it. the STRANGE thing is that this jump most often ...Boot : Sram Problem

spartan-3 sram

mete - 2004-09-22 11:55:00
Hi, Can you provide me a code piece to use async. sram e.g. in spartan-3 starter kit ? I could not get it work. Thanks in advance. Mete ...spartan-3 sram

auto reset / rs 232

fbob - 2009-02-02 14:22:00
Hi everyone, I have 2 unrelated questions: 1) I have a Xilinx ML505 board and I am looking for a way to make my SRAM power cycle automatically. Ideally I would like the SRAM to power off, then power on again after 30 seconds or more. Is there any way to have either the SRAM individually, or...auto reset / rs 232

Prototyping board with 4+ MB SRAM?

2003-11-04 04:40:00
Hello, Does anyone happen to know of a stock FPGA prototyping board with (a) onboard oscillator, (b) Ethernet and (c) at least 4 MB of SRAM? I have a need for such a board in a configuration which needs to support a very large range of input frequencies, hence I would prefer using SRAM; how...Prototyping board with 4+ MB SRAM?

Reading back SRAM content via JTAG?

moe - 2003-11-14 00:11:00
I hope I'm posting it in the right groups. I've been designing for a while, but with minimal JTAG knowledge. Q: Can I use JTAG interface to verify what I wrote into the SRAM, instead of the traditional read-back method? My setup and the reason for wanting to do it this way is : An FPGA in...Reading back SRAM content via JTAG?

Writing to Spartan 3 SRAM

2005-08-26 07:32:00
Hello all, i am very new to FPGA design and struggling to understand how to write data to Spartan 3 SRAM. I am using verilog and my code looks like something bleow, ------------------------------------------------------------------- cs = 1'b0; ub = 1'b0; lb = 1'b0; we = 1'b0; oe = 1'b1; ...Writing to Spartan 3 SRAM

where can I find the simulation model of the sram, ISSI61LV25616?

moo - 2006-03-17 12:12:00
Hello,Everbody!!! I'm working with the spartan3 starter kit,I want to use the on-board sram for temporary data storage,so I hope to find the simulation model of the sram(ISSI61LV25616-10T) for function and timing simulation .Please! Somebody tell me where I can find the simulation model,or anybody ...where can I find the simulation model of the sram, ISSI61LV25616?

Re: The littlest CPU

Jim Granville - 2008-07-20 17:24:00
rickman wrote: > On Jul 19, 2:57 am, Antti wrote: > > hi I may have different interests, yes smallest nonserialized CPU > > as for your current task is one of the wishes, and here also there > > is no one definitive winner > I read your thread about the serial processor and it was...Re: The littlest CPU

Spartan 3 Ram Instantiation

2005-09-02 16:35:00
Hey Folks, i have a question about the RAM instantiations for the Spartan 3(XC3S200) in the Xilinx verilog templates. You can instantiate different types of SRAM sizes and bit widths, like 16K x 1, 2K x 8, 512K x 32, but what if a user wants use the SRAM in a 256K x 16 format, or som...Spartan 3 Ram Instantiation

IP core design for FPGA

danialgifani - 2011-01-08 08:27:00
> Dear my friends > actually i want to design the SRAM IP core for FPGA , i have one SRAM cell schematic and layout for different technology 90nm,.. first i need to generate benchmark for that or if find available bench mark to use this cell instead current cell then can verify my sram and then s...IP core design for FPGA

Virtex-5 DDRII SRAM Calibration Issues

Colin - 2009-04-01 15:54:00
Hi guys, I'm trying to use a MIG v2.3 generated DDRII SRAM controller to verify our hardware for a 36 Mb, x18, Burst length 4, GSI SRAM chip. We're using a Virtex-5 LX110T chip with a 1738 package size. The design passes stage 1 calibration but hangs during stage 2 calibration. The same behavi...Virtex-5 DDRII SRAM Calibration Issues

FPGA SRAM

Carlos - 2003-12-26 15:41:00
Hi, Does anyone know how much SRAM is available on the XILINX XC2S300E SPARTAN IIE FPGA? Am I right in thinking it's 8096K Bytes? I'm planning on using the RAM32X1S module, I was wondering how many can I have inside a single FPGA. Thanks for any help, ...FPGA SRAM

xilinx bootloader help...

Dave - 2006-09-02 19:38:00
I'm using an ML403 development board. The board has a Compact Flash card on it, as well as SRAM, DDR RAM, Flash, etc. I'm trying to load my large application into a file that I can copy to the Compact Flash in a file. I want to have a bootloader program read then file, load it into SRAM, and...xilinx bootloader help...
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